adc14161 National Semiconductor Corporation, adc14161 Datasheet - Page 8

• Manufacturer Part Number: adc14161
• Description: Low-distortion, Self-calibrating 14-bit, 2.5 Msps, 390 Mw A/d Converter
• Manufacturer: National Semiconductor Corporation

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t
t
t
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AC Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND I/O = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (
TQFP,
device under normal operation will typically be about 410 mW (390 mW quiescent power + 20 mW due to 1 TTL load on each digital output. The values for maximum
power dissipation listed above will be reached only when the ADC14161 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5k
Note 6: See AN450, Surface Mounting Methods and Their Effect on Product Reliability , or the section entitled Surface Mount found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5V above V
is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above V
V
OD
EOCL
DATA_VALID
AD
ON
OFF
CAL
Note 8: To guarantee accuracy, it is required that V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Tested limits are guaranteed to Nationsl’s AOQL (Average Outgoing Quality Level).
Note 12: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 14: Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package) or the
LM4041CIZ-ADJ (TO-92 package), bandgap voltage reference is recommended for this application.
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
PD = +5V, V
Boldface limits apply for T
DC
Symbol
, the full-cale input voltage must be 4.85V
ESD Protection Scheme for Digital Input pins
JA
is 70˚C/W, so P
REF +
Falling edge of CLK to Data
Valid
Falling edge of CLK to falling
edge of EOC
Falling edge of CLOCK to Data
Valid
Aperture Delay
RD low to data valid on D00
-D13
RD high to D00 -D13 in
TRI-STATE
Calibration Time
= +2.0V, V
D
MAX = 1,785 mW at 25˚C and 982 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
A
= T
REF
A
Parameter
REF IN
J
= T
JA
= 25˚C, and represent most likely parametric norms.
= (V
), and the ambient temperature (T
J
REF
= AGND, f
= T
DC
+ − V
to ensure accurate conversions
MIN
A
DS100154-11
and V
REF
to T
J
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
−) given as +2.0V, the 14-bit LSB is 122 µV.
D
CLK
be connected together and to the same power supply with separate bypass capacitors at each V
MAX
(Continued)
= 2.5 MHz, RS = 25 , C
: all other limits T
IL
= 0.4V for a falling edge and V
A
Conditions
resistor. Machine model is 220 pF discharged through ZERO
), and can be calculated using the formula P
8
IN
ESD Protection Scheme for Analog Input and Digital
<
AGND or V
A
= T
A
A
J
or to 5V below GND will not damage this device, provided current
or below GND by more than 100 mV. As an example, if V
IN
+
L
= 25˚C(Notes 7, 8, 9)
IH
= V
>
= 50 pF/pin. After Auto-Cal
V
= 2.4V for a rising edge. TRI-STATE output voltage is forced
A
A
(Note 10)
or V
1/(4f
1/(8f
Typical
= V
110
Output pins
D
50
23
25
9
), the current at that pin should be limited to 25 mA.
D
CLK
CLK
= +5.0V, V
)
)
D
MAX = (T
(Note 11)
Limits
D
130
90
38
95
33
33
I/O = 3.0V or 5.0V,
DS100154-12
J
max - T
@
Temperature.
.
A
)/
JA
. In the 52-pin
(Limits)
ns(max)
ns(max)
ns(max)
ns(max)
ns(min)
ns(min)
Units
ms
ns
ns
A
is 4.75
+
pin.