cs5460 Cirrus Logic, Inc., cs5460 Datasheet - Page 24

• Manufacturer Part Number: cs5460
• Description: Single Phase Bi-directional Power/energy Ic
• Manufacturer: Cirrus Logic, Inc.

4.8 Timebase Calibration
4.9 Status Register and Mask Register
24
MSB
2
0
PWOR
Default** = 1.000
The Timebase Register is initialized to 1.0 on reset, allowing the device to function and perform computations.
The register is user loaded with the clock frequency error to compensate for a gain error caused by the crys-
tal/oscillator tolerance. The value is in the range 0.0
Address:
Default** = 0x000001 (Status Register)
The Status Register indicates the condition of the chip. In normal operation writing a ’1’ to a bit will cause the bit
to go to the ’0’ state. Writing a ’0’ to a bit will maintain the status bit in its current state. With this feature the user
can simply write back the status register to clear the bits that have been seen, without concern of clearing any
newly set bits. Even if a status bit is masked to prevent the interrupt, the status bit will still be set in the status
register so the user can poll the status.
The Mask Register is used to control the activation of the INT pin. Placing a logic ’1’ in the mask register will
allow the corresponding bit in the status register to activate the INT pin when the status bit becomes active.
IC
LSD
IOD
VOD
WDT
EOOR
Address: RA[4:0]* = 0x0D
DRDY
Res
23
15
7
2
-1
RA[4:0]* = 0x0F (Status Register)
RA[4:0]* = 0x1A (Mask Register)
0x000000 (Mask Register)
2
-2
EOUT
IROR
Res
22
14
Can be deactivated only by sending a port initialization sequence to the serial port. When writing
to status register this bit is ignored.
an input above Full Scale.
an input above Full Scale.
seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy register, then write
to the status register with this bit set to logic ’1’.
output rate that is too small for the power being measured. The problem can be corrected by
specifying a higher frequency in the pulse-rate register.
Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command.
Low Supply detect. Set when the PFMON pin falls below 2.5 volts with respect to the VA- pin.
Modulator oscillation detect on the current channel. Set when the modulator oscillates due to
Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to
Watch-Dog Timer. Set when there has been no reading of the Energy register for more than 5
EOUT energy/current summing register went out of range. This can be caused by having an
6
2
-3
2
-4
VROR
EDIR
WDT
21
13
5
2
-5
2
-6
EOR
VOD
Res
20
12
4
2
-7
TBC
.....
EOOR
MATH
IOD
19
11
3
2.0.
2
-17
2
-18
LSD
Res
Res
18
10
2
2
-19
2
-20
IOR
Res
17
9
1
0
2
-21
CS5460
2
-22
DS279PP5
VOR
Res
16
IC
8
0
LSB
2
-23