cs5460 Cirrus Logic, Inc., cs5460 Datasheet - Page 27

• Manufacturer Part Number: cs5460
• Description: Single Phase Bi-directional Power/energy Ic
• Manufacturer: Cirrus Logic, Inc.

gy register is read every second. As a result, the
WDT will not time out. Other applications, that
want to use the watchdog timer, will need to ensure
that the Energy register is read at least once in ev-
ery 5 second span.
5.2 Oscillator Characteristics
XIN and XOUT are the input and output, respec-
tively, of an inverting amplifier to provide oscilla-
tion and can be configured as an on-chip oscillator,
as shown in Figure 11. The oscillator circuit is de-
signed to work with a quartz crystal or a ceramic
resonator. To reduce circuit cost two load capaci-
tors C1 are integrated in the device, one between
XIN and DGND, one between XOUT and DGND.
Lead lengths should be minimized to reduce stray
capacitance. With these load capacitors the oscilla-
tor circuit is capable of oscillation up to 20 MHz.
To drive the device from an external clock source,
XOUT should be left unconnected while XIN is
driven by the external circuitry. There is an ampli-
fier between XIN and the digital section which pro-
vides CMOS level signals. This amplifier works
with sinusoidal inputs so there are no problems
with slow edge times.
DS279PP5
Figure 11. Oscillator Connection
DGND
XOUT
XIN
C1
C1
The CS5460 can be driven by a clock ranging from
2.5 to 20 MHz Table 2 shows the clock divide value
K (default = 1) that the CS5460 needs to be pro-
grammed with for normal operation.
5.3 Analog Inputs
The CS5460 accommodates a full scale range of
150 mV
bration can be used to increase or decrease the full
scale span of the converter as long as the calibra-
tion register values stay within the limits specified.
See the Calibration section for more details.
The current input channel has an input range of 30
mV
abled. This signal range is designed to handle low
level signals from a shunt sensor.
C1 = 22 pF
RMS
K
1
2
4
Table 3. CPU Clock (and K) Restrictions
RMS
when the internal x50 gain stage is en-
Oscillator
Circuit
on both input channels. System cali-
CLK (min)
MHz
2.5
10
5
CLK (max)
CS5460
MHz
10
20
5
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