tda8769hw/8 NXP Semiconductors, tda8769hw/8 Datasheet - Page 12

• Manufacturer Part Number: tda8769hw/8
• Description: 12-bit, 60/80/105 Msps Analog-to-digital Converter Adc Nyquist/high If Sampling
• Manufacturer: NXP Semiconductors

Philips Semiconductors
2. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
3. The ADC input range can be adjusted with an external reference connected to pin VREF. This voltage has to be
4. Output data acquisition: the output data is available after the maximum delay of t
5. The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
6. The total harmonic distortion is obtained with the addition of the first five harmonics.
7. The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
8. The effective number of bits, or ENOB, are obtained via a Fast Fourier Transform (FFT). The calculation takes into
9. Intermodulation measured relative to either tone with analog input frequencies of (tbf) and (tbf) MHz. The two input
10. IM2 is the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation
2003 Dec 09
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling
a) PECL mode 1: (DC level varies proportionally with V
b) PECL mode 2: (DC level varies proportionally with V
c) PECL mode 3: (DC level varies proportionally with V
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p)
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that
referenced to V
full-scale sine wave.
account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise
and distortion, or SINAD, is given by SINAD = ENOB
signals have the same amplitude and the total amplitude of both signals provides full-scale input to the converter
( 6 dB below full-scale for each input signal).
product. IM3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order
intermodulation product.
the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via
a 100 nF capacitor.
the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the
CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended
to decouple the CLKN or CLK input to DGND via a 100 nF capacitor.
case CLKN pin has to be connected to the ground.
CCA
.
12
6.02 + 1.76 dB.
CCD
CCD
CCD
) CLKN input is at PECL level and sampling is taken on
) CLK and CLKN inputs are at differential PECL levels.
) CLK input is at PECL level and sampling is taken on
d(s)
.
Objective specification
TDA8769