tda8002at/5/c2 NXP Semiconductors, tda8002at/5/c2 Datasheet - Page 8

• Manufacturer Part Number: tda8002at/5/c2
• Description: Ic Card Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 1 Clock circuitry definition
Notes
1. X = don’t care.
2. In low-power mode.
3. f
I/O circuitry
The three I/O transceivers are identical. The state is HIGH
for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and
AUX2UC). Pin I/O is referenced to V
V
The first side on which a falling edge is detected becomes
a master (input). An anti-latch circuitry first disables the
detection of the falling edge on the other side, which
becomes slave (output).
After a delay time t
the master side is transferred on the slave side.
1997 Nov 04
handbook, full pagewidth
DD
IC card interface
, thus ensuring proper operation in case V
int
LOW
MODE
= 32 kHz in low-power mode.
HIGH
HIGH
HIGH
HIGH
HIGH
(2)
I/OUC
I/O
d
(about 50 ns), the logic 0 present on
CLKSEL
HIGH
LOW
LOW
LOW
LOW
X
t d
(1)
CC
and pin I/OUC to
Fig.6 Master and slave signals.
CLKDIV1
CC
HIGH
HIGH
LOW
LOW
X
X
(1)
(1)
t d
V
DD
.
8
When the input is back to HIGH level, a current booster is
turned on during the delay t
both sides are back to their idle state, ready to detect the
next logic 0 on any side.
In case of a conflict, both lines may remain LOW until the
software enables the lines to be HIGH. The anti-latch
circuitry ensures that the lines do not remain LOW if both
sides return HIGH, regardless of the prior conditions.
The maximum frequency on the lines is approximately
1 MHz.
CLKDIV2
HIGH
HIGH
LOW
LOW
X
X
(1)
(1)
t d
conflict
FREQUENCY
STOP LOW
STOP LOW
STROBE
OF CLK
1
1
1
4
2
2
f
f
d
f
xtal
xtal
int
on the output side and then
idle
MGD703
Product specification
FREQUENCY
TDA8002
OF CLKOUT
1
1
2
f
f
f
f
f
2
xtal
xtal
xtal
xtal
int
f
int
(3)