tda8004t-c1 NXP Semiconductors, tda8004t-c1 Datasheet - Page 6

• Manufacturer Part Number: tda8004t-c1
• Description: Ic Card Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
TDA8004T_4
Product data sheet
8.2 Voltage supervisor
8.3 Clock circuitry
For generating a 5 V
incorporated. This step-up converter should be separately supplied by V
(from 4.5 V to 6.5 V). Due to large transient currents, the 2
step-up converter should have an ESR less than 100 m and be located as near as
possible to the IC.
The supply voltages V
This block surveys the V
used internally for maintaining the IC in the inactive mode during powering up or powering
down of V
As long as V
on the command lines. This also lasts for the duration of t
higher than V
The system controller should not try to start an activation during this time.
When V
The clock signal (CLK) to the card is either derived from a clock signal input on pin XTAL1
or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2.
The frequency may be chosen at f
CLKDIV2 (see
The frequency change is synchronous, which means that during transition, no pulse is
shorter than 45 % of the smallest period and that the first and last clock pulse around the
change has the correct width.
In the case of f
In order to reach a 45 % to 55 % duty factor on pin CLK the input signal on XTAL1 should
have a duty factor of 48 % to 52 % and transition times of less than 5 % of the input signal
period.
If a crystal is used with f
on the layout and on the crystal characteristics and frequency.
Fig 3. ALARM as a function of V
DD
(internal signal)
DD
falls below V
ALARM
DD
(see
th2
V
XTAL
Table
DD
is less than V
+ V
Figure
, the duty factors are dependent on the signal at XTAL1.
hys(th2)
4).
Rev. 04 — 20 February 2006
DD
5 % V
th2
XTAL
DD
3).
and V
.
, a deactivation sequence of the contacts is performed.
supply. A defined reset pulse of approximately 10 ms (t
, the duty factor on pin CLK may be 45 % to 55 % depending
CC
th2
DDP
supply to the card, an integrated voltage doubler is
+ V
DD
XTAL
may be applied to the IC in any time sequence.
hys(th2)
(t
W
,
1
= 10 ms)
t
2
W
f
, the IC will remain inactive whatever the levels
XTAL
,
1
4
f
XTAL
or
W
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
t
W
8
after V
f
100 nF capacitors of the
XTAL
via pins CLKDIV1 and
DD
TDA8004T
V
V
has reached a level
th2
th2
IC card interface
+ V
DDP
hys(th2)
mgm176
and PGND
W
6 of 26
) is