tda8026 NXP Semiconductors, tda8026 Datasheet - Page 29

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
The card clock frequency and the stop state are configured using the CLKDIV[1:0] and
CLKPD[1:0] bits. Refer to
Table 33
Table 32.
Table 33.
[1]
f
card slot number.
During transitions, no pulse is shorter than 45 % of the smallest period and both the
first/last clock pulse around the change have the correct width; making the frequency
change synchronous.
When changing the card clock frequency from one f
the modification is only active after the next rising clock edge.
Any change after switching the card clock frequency from an external f
division to the internal oscillator frequency (f
indicated by the state of the CLKSW bit (see the register descriptions in
Table
equal to 6.25 MHz.
PWDN bit
0
0
0
0
1
1
1
1
PWDN bit
logic 1 at activation sequence start
logic 1 at activation sequence start
logic 0 at activation sequence start
clk(ext)
•
•
If the PDWN bit is set to logic 0 at the start of the activation, the card clock value is the
CLKIN1 pin frequency for card slot 1 and the CLKIN2 pin frequency for card slots 2
to 5. If CLKDIV[1:0] = 00, the first four clock cycles are not transferred to CLK
When CLKDIV[1:0] = 01, 10 or 11, the first five clock cycles are not transferred to
CLK
If the PDWN bit is set to logic 1 at the start of the activation, the clock uses the
CLKPD1 bit.
If CLKDIV[1:0] = 00, the first four clock cycles are not transferred to CLK
the first five clock cycles are not transferred to CLK
22). In addition, it is assumed that the f
is the clock input frequency on either pin CLKIN1 or pin CLKIN2 depending on the
(n)
for synchronous mode.
.
Asynchronous mode card clock settings
Synchronous mode card clock settings
All information provided in this document is subject to legal disclaimers.
CLKDIV[1:0] bit
00
01
10
11
-
-
-
-
Rev. 1 — 9 March 2010
Table 32
[1]
for the configuration in asynchronous mode and
CLKDIV[1:0] bit CLKPD[1:0] bit Card clock (CLK)
-
-
-
osc(int)
(n)
clk(ext)
CLKPD[1:0] bit
-
-
-
-
00
01
10
11
.
) is not immediate. The change is
/ x frequency division is less than or
Multiple smart card slot interface IC
clk(ext)
x0
x1
xx
frequency division to another,
(n)
. When CLKDIV[1:0] is not 00,
Card clock (CLK)
f
f
f
f
logic 0
logic 1
f
f
clk(ext)
clk(ext)
clk(ext)
clk(ext)
clk(ext)
logic 0
logic 1
f
osc int
clk(ext)
TDA8026
clk(ext)
© NXP B.V. 2010. All rights reserved.
Table 11
/ 2
/ 4
/ 5
/ x (no change)
2
frequency
(n)
and
29 of 59
.