kad5512p-21 ETC-unknow, kad5512p-21 Datasheet - Page 18

• Manufacturer Part Number: kad5512p-21
• Description: 12-bit, 500msps A/d Converter
• Manufacturer: ETC-unknow

The power down mode can also be controlled
through the SPI port, which overrides the NAPSLP pin
setting. Details on this are contained in the Serial Pe-
ripheral Interface section. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin.
Data Format
Output data can be presented in three formats:
two’s complement, Gray code and offset binary. The
data format is selected via the OUTFMT pin as shown
in Table 4.
The data format can also be controlled through the
SPI port, which overrides the OUTFMT pin setting. De-
tails on this are contained in the Serial Peripheral In-
terface section.
Offset binary coding maps the most negative input
voltage to code 0x000 (all zeros) and the most posi-
tive input to 0xFFF (all ones). Two’s complement cod-
ing simply complements the MSB of the offset binary
representation.
When calculating Gray code the MSB is unchanged.
The remaining bits are computed as the XOR of the
current bit position and the next most significant bit.
Figure 37 shows this operation.
Converting back to offset binary from gray code
must be done recursively, using the result of each bit
for the next lower bit as shown in Figure 38.
Rev 0.5.1 Preliminary
KAD5512P-50
Figure 37. Binary to Gray Code Conversion
OUTFMT Pin
Table 4. OUTFMT Pin Settings
AVDD
AVSS
Float
Two’s Complement
Offset Binary
Gray Code
Mode
Mapping of the input voltage to the various data for-
mats is shown in Table 5.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facili-
tate configuration of the device and to optimize per-
formance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) and serial data input/output
(SDIO). The maximum SCLK rate is equal to the ADC
sample rate (f
tions and f
250MHz, maximum SCLK is 15.63MHz for writing and
3.79MHz for write operations. There is no minimum
SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance
Table 5. Input Voltage to Output Code Mapping
–Full Scale
–Full Scale
Mid–Scale
+Full Scale
+Full Scale
Voltage
+ 1LSB
– 1LSB
Input
Figure 38. Gray Code to Binary Conversion
SAMPLE
000000000000
000000000001
111111111110
111111111111
100000000000
SAMPLE
Binary
Offset
divided by 66 for reads. At f
) divided by 16 for write opera-
Complement
100000000000
100000000001
000000000000
011111111110
011111111111
Two’s
000000000000
000000000001
110000000000
100000000001
100000000000
Code
Gray
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SAMPLE
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