kad5512p-21 ETC-unknow, kad5512p-21 Datasheet - Page 21

• Manufacturer Part Number: kad5512p-21
• Description: 12-bit, 500msps A/d Converter
• Manufacturer: ETC-unknow

Bit 4
Bits 3:0 These bits should always mirror bits 4:7 to
Address 0x02: burst_end
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redun-
dant addressing. In 3-wire SPI mode the burst is
ended by pulling the CSB pin high. If the device is
operated in 2-wire mode the CSB pin is not available.
In that case, setting the burst_end address deter-
mines the end of the transfer. During a write opera-
tion, the user must be cautious to transmit the correct
number of bytes based on the starting and ending
addresses.
Bits 7:0 Burst End Address
DUT Information
Address 0x08: chip_id
Address 0x09: chip_version
The generic die identifier and a revision number, re-
spectively, can be read from these two registers.
Indexed DUT Configuration/Control
Address 0x10: device_index_A
Bits 1:0 ADC01, ADC00
A common SPI map, which can accommodate sin-
gle-channel or multi-channel devices, is used for all
Kenet ADC products. Certain configuration com-
mands (identified as Indexed in the SPI map) can be
executed on a per-converter basis. This register de-
termines which converter is being addressed for an
Indexed command. It is important to note that only a
single converter can be addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed.
Address 0x20: offset_coarse
Address 0x21: offset_fine
The input offset of the ADC core can be adjusted in
fine and coarse steps. Both adjustments are made
Rev 0.5.1 Preliminary
KAD5512P-50
Setting this bit high resets all SPI registers to
default values.
Reserved
This bit should always be set high.
avoid ambiguity in bit ordering.
This register value determines the ending ad-
dress of the burst data.
Determines which ADC is addressed. Valid
states for this register are 0x01 or 0x10. The two
ADC cores cannot be adjusted concurrently.
via an 8-bit word as detailed in Table 7. The data for-
mat is twos complement.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
Address 0x22: gain_coarse
Address 0x23: gain_medium
Address 0x24: gain_fine
Gain of the ADC core can be adjusted in coarse,
medium and fine steps. Coarse gain is a 4-bit adjust-
ment while medium and fine are 8-bit. The data for-
mat is twos complement for all three registers.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
Nominal Step Size
Mid–Scale (0x00)
+Full Scale (0x7F)
–Full Scale (0x80)
Parameter
Steps
Table 8. Coarse Gain Adjustment
Nominal Step Size
–Full Scale (0x08)
Mid–Scale (0x00)
+Full Scale (0x07)
Table 7. Offset Adjustments
Parameter
Steps
Coarse Offset
0x20[7:0]
+23.8mV
-24.0mV
187.5µV
0.0mV
256
Coarse Gain
0x22[3:0]
-11.2%
+9.8%
0.0%
1.4%
16
Fine Offset
0x21[7:0]
+1.7mV
-1.7mV
13.3µV
0.0mV
256
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