hi7188 Intersil Corporation, hi7188 Datasheet
hi7188
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hi7188 Summary of contents
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... Extreme design complexity and excessive software overhead is eliminated. The HI7188 contains a fully differential 8 channel multiplexer, Programmable Gain Instrumentation Amplifier (PGIA), 4th order sigma-delta ADC, integrating filter, line noise rejection fi ...
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... Pinouts OSC OSC DV DGND INL1 V INH1 V INL2 V INH2 V INL3 2 HI7188 HI7188 (MQFP) TOP VIEW MXC RST DGND ...
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Functional Block Diagram RHI RLO PHYSICAL CHANNELS V IN1H V IN2H V IN3H V IN4H V IN5H V IN6H V IN7H V IN8H INTEGRATING 4TH 1 ORDER PGIA MODULATOR V IN1L V IN2L V IN3L PGIA ...
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... CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL 8 - -5V 4 HI7188 3.6864MHz 1 26 OSC 0 HI7188IN 25 +2.5V V RHI REFERENCE 24 V RLO 8 V INH1 7 V INL1 10 V INH2 9 V INL2 12 V INH3 11 V INL3 14 V INH4 13 V INL4 15 V INH5 14 V INL5 ...
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... I/O reset (active low) input. Resets serial interface state machine only Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and SDIO pins are three-state. 5 HI7188 PIN DESCRIPTION and OSC 1 . The oscillator frequency should be 3.6864MHz to maintain Line 1 and OSC ...
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... Output Logic High Voltage Output Logic Low Voltage Output Three-State Leakage Current Digital Output Capacitance, C OUT 6 HI7188 Thermal Information Thermal Resistance (Typical, Note 1) MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Storage Temperature Range . . . . . . . . . .- Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 SS DD Maximum Lead Temperature (Soldering 10s 300 ...
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... Fully differential input signal source is used. 7. See Load Test Circuit, Figure 10k , For Line Noise Rejection, 3.6864MHz is required to develop internal clocks to reject 50/60Hz. 9. SLP is the sleep mode enable bit defined in bit 3 of the Control Register (CR <3>). 7 HI7188 = +5V -5V +5V +2.5V RHI = 3 ...
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... STRAY L CAPACITANCE) FIGURE 1. LOAD TEST CIRCUIT 2 DUT = 200pF FIGURE 3. CHARGE DEVICE MODEL ESD TEST CIRCUIT t PRE SCLK SCLKPW SCLKPW DSU t DHLD 1ST BIT FIGURE 4. DATA WRITE TO HI7188 R 1 DUT DIELECTRIC CHARGED DEVICE MODEL 2ND BIT ...
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... DV FIGURE 5. DATA READ FROM HI7188 5 6 FIGURE 6. DATA READ FROM HI7188 Input Span - The input span defines the minimum and maximum input voltages the device can handle while still calibrating properly for gain. End of Scan (EOS) - The end of scan is a signal used to indicate all active logical channels have been converted and data is available to be read ...
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... When the HI7188 is powered up it needs to be reset by pulling the RST line low. This resets the internal registers as shown in Table 1. This initial configuration defines the part for one ...
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... HI7188 in the event of power failure or reset. Analog Section Description The analog portion of the HI7188 consists fully differential Multiplexer, Programmable Gain Instrumentation amplifier (PGIA) and a 4th order Sigma-Delta modulator. Please refer to the simplified analog block diagram in Figure 8. ...
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... HI7188 analog circuitry and should always be tied to the midpoint of the AV provides a common mode input voltage for the internal operational amplifiers and must be driven from a low noise, low impedance source not tied to analog ground. Failure will result in degraded HI7188 performance. DATA CHAN CONVERSION CALIBRATION SWITCH ...
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... The HI7188 has the ability to do the same function as the Integrating ADC but samples the input four times during the line cycle (see Figure 12). For this discussion, the desired analog input signal will be zero. The HI7188 accomplishes this by instituting a four quadrant, four point running average system ...
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... Samples S2 and S4 (180 degrees later) will have the equal magnitudes but opposite signs. 6. The HI7188 sums the samples S1, S3, S2 and S4 which results in averaging the line noise signal to zero. 7. These four samples are placed, real time, in the 4x8 array of registers used for LNR ...
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... System Positive Full Scale Calibration The system positive full scale calibration mode is a process that allows the user to lump positive gain errors of external circuitry and the internal gain errors of the HI7188 together to EACH calculate the positive transfer function of the system. This ...
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... In unipolar mode, only binary coding is available and the two’s complement coding bit is a don’t care. The output coding for the HI7188 is shown in Tables 4 and 5. V represents the applied zero scale input during system ZS offset calibration ...
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... RAM0 and the write pointer remains with RAM1. This has the effect of overwriting conversion N+1 with N+2 before N+1 can be read, therefore conversion N+1 is lost. Clocking/Oscillators The master clock of the HI7188 can be supplied by either a crystal connected between the OSC 1 shown in Figure 13A or a CMOS compatible clock signal ...
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... Example 2. The physical channel conversion order as specified by the CCRs The HI7188 is setup via the Control Register to convert only 3 logical channels. The IR byte written is 1xx01101 (write the offset RAM) ...
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... CR, start byte 0, 2 byte transfer 0/1 00 0001 CR, start byte 1, 1 byte transfer 0/1 01 0001 CR, start byte 1, 2 byte transfer 0/1 00 0100 CCR #1, start byte 0, 1 byte transfer 0/1 00 0101 CCR #1, start byte 1, 1 byte transfer 19 HI7188 TABLE 7. INTERNAL REGISTER ADDRESS (Continued) R/W IR [7] IR [6:5] 0/1 0/1 0/1 0 LSB 0 0/1 0/1 ...
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... SDIO pin while data out uses the SDO pin. This bit is low (two-wire, SDIO exclusively) after RESET is applied. Channel Configuration Registers The HI7188 Channel Configuration Registers (CCR) comprise a 64-bit memory element that defines the logical channel conversion order as well as each logical channel specific data ...
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... MCS51 and MCS96 family of microcontrollers, or other similar processors. SCLK. Serial Clock. The serial clock pin is used to synchronize data to and from the HI7188 and to run the port state machines. In Synchronous External Clock Mode, SCLK is configured as an input, is supplied by the user, and can run 5MHz rate ...
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... IR cycle. Serial Interface Communication It is useful to think of the HI7188 interface in terms of communication cycles. Each communication cycle happens in 2 phases. The first phase is the writing of an instruction byte while the second phase is the data transfer as described by the instruction byte ...
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... METALLIZATION: Type: AlSiCu Å Thickness:Metal 2 16k Å Metal 1 6k SUBSTRATE POTENTIAL Metallization Mask Layout 23 HI7188 PASSIVATION: Type: Sandwich Å Nitride Thickness: 8k Å USG Thickness: 1k WORST CASE CURRENT DENSITY <2 A/cm PROCESS: HBCIO HI7188 ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 24 HI7188 Q44.10x10 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL -B- e SEATING PLANE A NOTES: 1 ...