hi7188 Intersil Corporation, hi7188 Datasheet - Page 15

• Manufacturer Part Number: hi7188
• Description: 8-channel, 16-bit, High Precision, Sigma-delta A/d Sub-system
• Manufacturer: Intersil Corporation

imperative that the zero-scale calibration be performed
before either of the gain calibrations. The order of the gain
calibrations is not important. Non-calibrated data can be
obtained from the device by writing 000000 (h) to the Offset
Calibration Register, 800000 (h) to the Positive Full Scale
Calibration Register, and 800000 (h) to the Negative Full
Scale Calibration Register. This sets the offset of the part to
0 and both the positive and negative gain slope factors to 1.
A calibration routine should be initiated whenever there is a
change in the ambient operating temperature or supply
voltage. It should also be initiated if there is a change in the
gain, bipolar, or unipolar input range.
The user may choose to ignore data during calibration or
check whether any ACTIVE channel is in calibration. Bit 12,
the SE bit, of the Control Register offers capability to
suppress the EOS interrupt during calibration. If the SE bit is
high the EOS interrupt will be suppressed if any active
logical channel is in the calibration mode. If the SE bit is high
and no active logical channels are in the calibration mode
the EOS interrupt will function normally. If low, the suppress
EOS function is disabled. To check whether any logical
channel is in calibration the user can monitor the Calibration
Active (CA) output pin. The CA output pin is high when at
least one of the active logical channels are in calibration. If a
non active logical channel is in calibration the CA will not be
high. The user can monitor the CA pin to determine when all
active logical channels are calibrated.
NOTE: When the user accesses the calibration RAMs, via the Serial
Interface, the conversion process stops, resetting the modulator,
integrating filter and clearing the EOS interrupt. When the calibration
RAM I/O operation is completed the device automatically restarts
beginning on logical channel 1. The contents of the CR and CCR are
not affected by this I/O.
Calibration Time
The calibration time varies depending several factors
including LNR (50Hz/60Hz) being enabled or disabled, and 2
point calibration. Table 3 contains a summary of the
conversion time depending on these factors. Since line noise
rejection is a major factor this discussion is divided
accordingly.
NOTE: N is the number of active channels. Total Cal column
assumes zero switching time between calibration points.
LNR
On
On
On
On
Off
Off
FREQ
LNR
(Hz)
n/a
n/a
50
50
60
60
TABLE 3. CALIBRATION TIME
ACTIVE
CHANS
n/a
n/a
n/a
n/a
N
N
PNTS
CAL
15
2.5
2
3
2
3
2
3
20
20
16.7
16.7
N (0.4803)
N (0.4803)
POINT
EACH
CAL
(ms)
40
60
33.3
50.0
2N (0.4803)
3N (0.4803)
TOTAL
CAL
(ms)
HI7188
Line Noise Rejection On
When line noise rejection is enabled, it takes 4 conversion
scan periods to fill the averaging filters used for attenuating
the periodic line noise. A conversion scan involves
converting all 8 logical channels at a rate dependent on
whether LNR is set to 50Hz or 60Hz. The scan period is 5ms
(1/200Hz) and 4.167ms (1/240Hz) respectively. The number
of active channels is not applicable in this calculation since
the microsequencer converts on ALL logical channels to
maintain LNR timing regardless of the number of user
defined active channels.
Line Noise Rejection Off
Operation of the device is altered slightly when LNR is
disabled. Since the microsequencer is not synchronizing for
any line noise, the conversion rate increases to 260.3
conversions second/channel (10% increase). With LNR
disabled, a conversion scan involves converting only the
ACTIVE logical channels. When ACTIVELY converting on
less than 8 channels, this is the major speed advantage over
LNR enabled which sets conversion scan period based on
ALL eight logical channels. Refer to Table 3.
System Offset Calibration
The system offset calibration mode is a process that allows
the user to lump offset errors of external circuitry and the
internal errors of the HI7188 together and null them out. This
mode will convert the external differential signal applied to
the V
calibration RAM for that physical channel. To invoke the
system offset calibration the user applies the “zero scale”
voltage to the physical channel requiring calibration, then
writes the related CCR byte indicating offset calibration is
required. The next time this logical channel is converted, the
microsequencer performs calibration and updates the
related offset RAM. Next the internal microsequencer places
that logical channel back into the conversion mode and
updates the CCR byte.
System Positive Full Scale Calibration
The system positive full scale calibration mode is a process
that allows the user to lump positive gain errors of external
circuitry and the internal gain errors of the HI7188 together to
calculate the positive transfer function of the system. This
mode will convert the external differential signal applied to the
V
Scale calibration RAM for that physical channel. To invoke the
system positive full scale calibration the user applies the
“positive full scale” voltage to the physical channel requiring
calibration, then writes the related CCR byte indicating
positive full scale calibration is required. The next time this
logical channel is converted, the microsequencer performs
calibration and updates the related system positive full scale
calibration RAM. Next the internal microsequencer places that
logical channel back into the conversion mode and updates
the CCR byte.
IN
inputs and then store that value in the system positive full
IN
inputs and then store that value in the offset