ad875 Analog Devices, Inc., ad875 Datasheet - Page 10

• Manufacturer Part Number: ad875
• Description: 10-bit, Cmos Converter
• Manufacturer: Analog Devices, Inc.

AD875
Also, a sleep mode feature is provided such that for STBY =
HIGH and the clock disabled, the static power of the AD875
will drop below 50 mW. The AD875 reaches rated accuracy 4
clock cycles after STBY is brought LOW and the clock is
started.
DIGITAL OUTPUTS
Each of the on-chip buffers for the AD875 output bits (D0–D9,
OVR, UNR) is powered from the DRV
from AV
variety of logic families while minimizing the amount of glitch
energy generated. In all cases, a fan-out of one is recommended
to keep the capacitive load on the output data bits below the
specified 20 pF level.
For DRV
with both high speed CMOS and TTL logic families. For TTL,
the AD875 on-chip, output drivers were designed to support
several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below 15 MHz, other TTL
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD875 sustains 15 MHz operation with
DRV
for compatibility with the AD875 Digital Specification table.
THREE-STATE OUTPUTS
The digital outputs of the AD875 can be placed in a high
impedance state by setting the THREE-STATE pin to HIGH.
This feature is provided to facilitate in-circuit testing or
evaluation. Note that this function is not intended for enabling/
disabling the ADC outputs from a bus at 15 MHz. Also, to
avoid corruption of the sampled analog signal during conversion
(three clock cycles), it is highly recommended that the AD875
outputs be enabled on the bus prior to the first sampling. For
the purpose of budgetary timing, the maximum access and float
delay times (t
150 ns.
OUT OF RANGE
As Table II indicates, an Underrange (UNR) or Overrange
(OVR) condition exists when the analog input voltage is beyond
the input range (nominally +2 V to +4 V) of the converter.
UNR (Pin 46) is set LOW when the analog input voltage is within
the analog input range. UNR is set HIGH (after accounting for
pipeline latency) and will remain HIGH when the analog input
voltage is less than the input range by 1/2 LSB from the center
THREE-STATE
Figure 14. High Impedance Output Timing Diagram
UNR, OVR
DD
D0–D9,
= 3.3 V. In all cases, check your logic family data sheets
DD
DD
or DV
= 5 V, the AD875 output signal swing is compatible
DD
, t
DD
HL
ACTIVE
. The output drivers are sized to handle a
shown in Figure 14) for the AD875 are
t
DD
HIGH IMPEDANCE
DD
supply pins, separate
t
HL
–10–
of the negative full-scale output code. OVR (Pin 47) is set LOW
when the analog input voltage is within the analog input range.
OVR is set HIGH (after accounting for pipeline latency) and
will remain HIGH when the analog input voltage is greater than
the input range by 1/2 LSB from the center of the positive
full-scale output code.
GROUNDING AND LAYOUT RULES
As is the case for any high performance device, proper grounding
and layout techniques are essential in achieving optimal
performance. The analog and digital grounds on the AD875
have been separated to optimize the management of return
currents in a system. It is recommended that a 4-layer printed
circuit board (PCB) which employs a ground plane and power
planes be used with the AD875. The use of ground and power
planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
2. The minimization of the impedance associated with ground
3. The inherent distributed capacitor formed by the power
These characteristics result in both a reduction of electromagnetic
interference (EMI) and an overall improvement in performance.
It is important to design a layout which prevents noise from
coupling onto the input signal. Digital signals should not be run
in parallel with the input signal traces and should be routed
away from the input circuitry.
Separate analog and digital grounds should be joined together
directly under the AD875. A solid ground plane under the
AD875 is also acceptable if care is taken in the management of
the power and ground return currents. A general “rule-of-thumb”
for mixed signal layouts dictates that the return currents from
digital circuitry should not pass through critical analog circuitry.
POWER SUPPLY DECOUPLING
The analog and digital supplies of the AD875 have been separated
to prevent the typically large transients associated with digital
circuitry from coupling into the analog supply (AV
The digital supplies have also been separated into DRV
DV
the AD875 and are likely to contain high energy transients.
Each power supply pin should be decoupled with a 0.1 F
capacitor located as close to the pin as possible. For optimal
performance, surface-mount capacitors are recommended. The
inductance associated with the leads of through-hole ceramic
capacitors typically render them ineffective at higher frequencies. A
complete system will also incorporate tantalum capacitors in the
10 F–100 F range to decouple low frequency noise and ferrite
beads to limit high frequency noise.
and its return path.
and power paths.
plane, PCB insulation, and ground plane.
DD
. The DRV
DD
pins provide power for the digital I/Os of
DD
).
DD
REV. 0
and