ad875 Analog Devices, Inc., ad875 Datasheet - Page 7

• Manufacturer Part Number: ad875
• Description: 10-bit, Cmos Converter
• Manufacturer: Analog Devices, Inc.

REV. 0
or equal to 75
impedance is suggested to minimize noise coupled on the AIN
inputs.
For systems which must level shift a ground-referenced signal in
order to comply with the input requirements of the AD875, a
circuit like Figure 6 is recommended. The suggested op amp, an
AD817 or AD818, is configured in inverting mode, where the ac
gain of the input signal is –1. The amount of dc-level shifting is
controlled by the dc voltage at the noninverting input of the op
amp. The REFBF signal is attenuated by a resistive voltage
divider and then multiplied by 2. In the case where REFBF =
1.6 V, the dc output level will be 2.6 V. The AD817 is a low
cost, fast settling, single-supply op amp with a 29 MHz unity
gain bandwidth. The AD818 is similar to the AD817 but has a
50 MHz unity gain bandwidth.
The AD875 samples the analog input voltage twice: once on the
rising edge of the clock (CLK) and once on the falling edge.
The first sample, taken on the rising edge, is used to perform a
coarse estimate of the input. As indicated in Figure 7, the
analog input voltage must be settled within V
final value at this time and must remain within V
second sample has been taken. The second sample, taken on the
falling edge of the clock, will determine the exact value digitized
and should be accurate to within 10 bits (0.1%). Note that the
actual sample points are delayed by t
For applications where step input signals are expected (i.e.,
CCD or multiplexed outputs), the settling time of the input
drive circuitry should be examined carefully. In most cases, the
settling time requirements placed on the input amplifier are
easily met by the AD817 or AD818. For higher speed operation,
it may be necessary to use faster op amps such as the AD810 or
AD811.
As a result of the AD875’s settling requirements, there is a
maximum slew rate limitation placed on the analog input signal.
For applications using CCDs and other sampled analog systems,
Figure 5. Simple AD875 Drive Requirements
Figure 6. DC Level Shift with Gain of –1
0V
dc
V
REFBF
is suggested (Figure 5). In general, a low drive
S
2V
p-p
R
IN
14.7k
3k
= 4.99k
75
2
3
AD817 OR
R
+V
AD818
f
7
4
= 4.99k
CC
S1
39
40
0.1µF
and t
AD875
AIN
AIN
NC
NC
1
5
S2
6
SE
.
( 16 mV) of its
SE
39
40
until the
AIN
AIN
AD875
–7–
the AD875 can be used directly. However, for continuous signal
applications, Figure 7 implies a maximum slew rate limitation
on the analog input:
where t
or one-half the full period when the clock is run with 50% duty
cycle. For example, at 15 MHz clock rate, the maximum slew
rate is about 0.48 V/ s. This corresponds to a maximum analog
input frequency of 76 kHz when a full-scale (2 V peak-to-peak)
sine wave is used. For input signals with higher slew rates, a
sample-and-hold amplifier must be used for accurate
digitization.
REFERENCE INPUT
Driving the Reference Terminals
The AD875 requires an external reference on pins REFTF and
REFBF. Reference sense pins REFTS and REFBS are also
provided for Kelvin connections to minimize voltage drops due
to external and internal wiring resistances. A resistor ladder
nominally 400
and REFBF.
The voltage drop across the internal resistor ladder determines
the input span of the AD875. The driving voltages required at
the REFTF and REFBF pins are nominally +4 V and +2 V
respectively resulting in a 2 V input span. In order to maintain
the requisite 2 V drop across the internal ladder, the external
reference must be capable of typically providing 5 mA of dc
current.
Transient current flows in and out of the REFTF and REFBF
pins. Therefore, a low ac impedance is required at these
terminals for proper operation. Bypassing each pin with suitable
capacitive decoupling should effectively attenuate any transients.
See the AD875 Evaluation Board Schematic for recommended
values. Mid (REFMID) and quarter (REFTQ, REFBQ) ladder
tap points are also available for additional decoupling if
required. It is important to note that these tap points cannot be
used to correct integral linearity as is sometimes done in a
typical flash converters.
There are several reference configurations suitable for the
AD875 depending on the application, desired performance and
cost trade-offs. The simplest configuration, shown in Figure 8,
utilizes a resistor string to generate the reference voltages from
the converter’s analog power supply. A 10 F tantalum
capacitor in parallel with a 0.1 F ceramic capacitor will provide
adequate decoupling for both the REFTF and REFBF pins.
The 0.1 F capacitors should be physically located within 1 cm
of REFTF and REFBF. A 10 F capacitor connected between
Slew Rate of Analog Input ( maximum )
CH
Figure 7. Analog Input Settling Requirement
CLK
AIN
is the “high” period of the sample clock in seconds,
V
COARSE
V
FINAL
is connected internally between pins REFTF
V
SE
t
S1
t
16 mV
S2
t
CH
AD875
( V /sec )