clc5612 National Semiconductor Corporation, clc5612 Datasheet - Page 15

• Manufacturer Part Number: clc5612
• Description: Dual, High Output, Programmable Gain Buffer
• Manufacturer: National Semiconductor Corporation

Application Division
Layout Considerations
A proper printed circuit layout is essential for achieving high
frequency performance. National provides evaluation boards
for the CLC5612 (CLC730038-DIP, CLC730036-SOIC) and
suggests their use as a guide for high frequency layout and
as an aid for device testing and characterization.
General layout and supply bypassing play major roles in high
frequency performance. Follow the steps below as a basis
for high frequency layout:
Evaluation Board Information
A data sheet is available for the CLC730038/CLC730036
evaluation boards. The evaluation board data sheets
provide:
The evaluation boards are designed to accommodate dual
supplies. The boards can be modified to provide dual
supplies. The boards can be modified to provide single
supply operation. For best performance; 1) do not connect
the unused supply, 2) ground the unused supply pin.
Special Evaluation Board Considerations for the
CLC5612
To optimize off-isolation of the CLC5612, cut the R
both the CLC730038 and the CLC730036 evaluation
boards. This cut minimizes capacitive feedthrough between
the input and the ouptut. Figure 13 shows where to cut both
evaluation boards for improved off-isolation.
•
• Place the 6.8µF capacitors within 0.75 inches of the
• Place the 0.1µF capacitors less than 0.1 inches from the
• Remove the ground plane under and around the part,
• Minimize all trace lengths to reduce series inductances.
• Use flush-mount printed circuit board pins for prototyping,
• Evaluation board schematics
•
• General information about the boards
both supplies.
power pins.
power pins.
especially near the input and output pins to reduce
parasitic capacitance.
never use high profile DIP sockets.
Include 6.8µF tantalum and 0.1µF ceramic capacitors on
Evaluation board layouts
(Continued)
f
trace on
15
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
The readme file that accompanies the diskette lists released
models and provides a list of modeled parameters. The
application note OA-18, Simulation SPICE Models for
National’s
reproduction of the readme file.
• Support Berkeley SPICE 2G and its many deriatives
• Reproduce typical DC, AC, Transient, and Noise
• Support room temperature simulations
730036 Top
( 9 7 0 ) 2 2 6 - 0 5 0 0
performance
OUT1
C4
+
FIGURE 13. Evaluation Board Changes
Cut traces here
Op
ROUT1
-Vcc
+Vcc
RF1
Amps,
C1
C2
C3
+
RF2
contains
RG1 RIN1
ROUT2
schematics
OUT2
RG2
IN1
RIN2
GND
www.national.com
IN2
DS015001-61
DS015001-52
and
a