clc5523 National Semiconductor Corporation, clc5523 Datasheet - Page 7

• Manufacturer Part Number: clc5523
• Description: Low-power, Variable Gain Amplifier
• Manufacturer: National Semiconductor Corporation

Minimizing Parasitic Effects on
Small Signal Bandwidth
The best way to minimize parasitic effects is to use the
small outline package and surface mount components.
For
specifically axial resistors, resistor self-capacitance
should be considered. Example: the average magnitude
of parasitic capacitance of RN55D 1% metal film
resistors is about 0.15pF with variations of as much as
0.1pF between lots.
bandwidth, these small parasitic reactance variations can
cause measurable frequency response variations in the
highest octave. We therefore recommend the use
of surface mount resistors to minimize these parasitic
reactance effects. If an axial component is preferred, we
recommend PRP8351 resistors which are available from
Precision Resistive Products, Inc., Highway 61 South,
Mediapolis, Iowa.
Small Signal Response at Low A
When the maximum gain, as set by R
than or equal to A
observed in the amplifier response. When the gain range
is set to less than A
be observed at higher frequencies. At gain ranges of
2 ² A
R
approximately 6dB in the upper octave.
If peaking is observed with the recommended R
and a small increase in the R
problem, then investigate the possible causes and
remedies listed below.
f
.
Capacitance across R
Capacitive Loads
Long traces and/or lead lengths between R
and the CLC5523
vmax
At gain ranges of A
designs
Do not place a capacitor across R
Keep traces connecting R
short as possible
Place a small resistor (20-50W) between the
output and C
Keep these traces as short as possible
² 10 peaking can be minimized by increasing
utilizing
vmax
L
= 10, little or no peaking should be
Given the CLC5523’s extended
vmax
through-hole
vmax
f
= 10, some peaking may
f
resistor does not solve the
f
< 2 peaking reaches
separated and as
vmax
g
and R
f
components,
f
, is greater
f
resistor,
f
7
Adjusting Offsets and DC Level Shifting
Offsets can be broken into two parts: an input-referred term
and an output-referred term. These errors can be trimmed
using the circuit in Figure 4. First set V
the trim pot R4 to null the offset voltage at the output. This
will eliminate the output stage offsets. Next set V
and adjust the trim pot R1 to null the offset voltage at the
output. This will eliminate the input stage offsets.
Long traces between CLC5523 and 0.1mF
bypass capacitors
Extra capacitance between the R
ground (C
Non-inverting input pin connected directly to
ground
+5V
10k
R1
-5V
Keep these traces less than 0.2 inches (5mm)
For the devices in the PDIP package, an
additional 1000pF monolithic capacitor should be
placed less than 0.1” (3mm) from the pin
See the Printed Circuit Board Layout sub-section
below for suggestions on reducing C
Increase R
reducing C
Place a 50 to 200W resistor between the non-
inverting pin and ground
0.1mF
Figure 4: Offset Adjust Circuit
10k
R2
G
)
f
G
V
if peaking is still observed after
in
R
g
25W
2
3
CLC5523
V
G
1
4
7
R3
10k
G
0.1mF
6
R
g
http://www.national.com
to 0V and adjust
f
pin and
G
+5V
-5V
R4
10k
V
o
G
to 2V