clc5523 National Semiconductor Corporation, clc5523 Datasheet - Page 8

• Manufacturer Part Number: clc5523
• Description: Low-power, Variable Gain Amplifier
• Manufacturer: National Semiconductor Corporation

High frequency op amp performance is strongly
dependent on proper layout, proper resistive termination
and adequate power supply decoupling. The most impor-
tant layout points to follow are:
Capacitively bypassing power pins to a good ground plane
with a minimum of trace length (inductance) is necessary
for any high speed device, but it is particularly important for
the CLC5523.
Evaluation boards are available for both the 8-pin DIP
and small outline package types. Evaluation kits that
contain an evaluation board and CLC5523 samples can
be obtained by calling National Semiconductor’s
Customer Service Center at 1-800-272-9959. The 8-pin
DIP evaluation kit part number is CLC730065. The 8-pin
small outline evaluation kit part number is CLC730066.
http://www.national.com
Use a ground plane
Bypass each power supply pin with these capacitors:
Establish wide, low impedance, power supply traces
For the plastic DIP package, a 25W resistor should
be connected from pin 4 to ground with a minimum
length trace
a high-quality 0.1mF ceramic capacitor placed
less than 0.2” (5mm) from the pin
a 6.8mF tantalum capacitor less than 2” (50mm)
from the pin
for the plastic DIP package, a high-quality
1000pF ceramic capacitor placed less than 0.1”
(3mm) from the pin
Control
Gain
50W
RX
* 25W series resistor is not required on the
small outline device and does not appear on
the small outline board
50W
R
Printed Circuit Board Layout
Signal
Input
in
100W
Figure 5: Evaluation Board Schematic
R
g
Evaluation Boards
25W
GND
*
V
V
R
G
in
g
X1
8
+
-
To minimize high frequency distortion, other layout issues
need be addressed:
The DIP evaluation kit has been designed to utilize axial
lead components. The small outline evaluation kit has
been designed to utilize surface mount components.
The circuit diagram shown in Figure 5, applies to both the
DIP and the small outline evaluation boards.
Minimize trace and lead lengths for components
I-
+V
V
-V
0.1mF
Minimize or eliminate sources of capacitance
between the R
adjacent feedthrough vias between the R
output leads since such a geometry may give rise
to a significant source of capacitance.
between the inverting and output pins
Remove ground plane 0.1” (3mm) from all
input/output pads
For prototyping, use flush-mount printed circuit
board pins; never use high profile DIP sockets
Short, equal length, low impedance power supply
return paths from the load to the supplies
avoid returning output ground currents near the
input stage.
o
CC
CC
1kWž
R
f
5V
6.8mF
0.1mF
50Wž
R
o
6.8mF
f
pin and the output pin. Avoid
Output
-5V
f
and