at84ad001b ATMEL Corporation, at84ad001b Datasheet - Page 17

• Manufacturer Part Number: at84ad001b
• Description: Dual 8-bit 1 Gsps Adc
• Manufacturer: ATMEL Corporation

Figure 11. Data Ready Reset
Figure 12. Data Ready Reset 1:1 DMUX Mode
Note:
2153C–BDC–04/04
DOIA[0:7] or
DOQA[0:7]
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset
occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then
only, remains in reset state (frozen to a low level in 1:1 DMUX mode). The next falling edge of the input clock after reset makes
the output clock return to normal mode (after TDR).
CLKOI or
CLKOQ
CLKI or
CLKI or
DDRB
CLKQ
DDRB
CLKQ
VIN
TA
1 ns min
FORBIDDEN
Clock in
1 ns min
2 ns
Reset
500 ps
N
ALLOWED
N + 1
TDR
TDR
Pipeline Delay + TDO
FORBIDDEN
500 ps
ALLOWED
N
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