pca9561 NXP Semiconductors, pca9561 Datasheet - Page 5

• Manufacturer Part Number: pca9561
• Description: Quad 6-bit Multiplexed I2c Eeprom Dip Switch
• Manufacturer: NXP Semiconductors

1. To ensure data integrity, the non-volatile register must be internally write protected when V
Philips Semiconductors
REGISTER DESCRIPTION
If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP
condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the
following STOP condition. Up to four bytes can be sent sequentially. If any more data bytes are sent after the second byte, they will not be
acknowledged and no bytes will be written to the non-volatile registers. After a byte is read from or written to the EEPROM, the part
automatically points to the next non-volatile register. If the command code was FFH, the MUX_IN values are sent with the three MSBs padded
with zeroes as shown below. If the command codes was 00H, then the non-volatile register 1 is sent, and if the command code was 01H, then
the non-volatile register 1 is sent.
EEPROM Byte 0 Register
EEPROM Byte 1 Register
EEPROM Byte 2 Register
EEPROM Byte 3 Register
MUX_IN Register
If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the
read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code.
The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s.
The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The
data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the
non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins.
After a valid I
the part will not acknowledge its address.
NOTE:
2004 May 17
Quad 6-bit multiplexed I
component is dropped below normal operating levels.
Default
Default
Default
Default
Write
Read
Write
Read
Write
Read
Write
Read
Read
2
C write operation to the EEPROM, the part cannot be addressed via the I
D7
D7
D7
D7
D7
X
X
X
X
0
0
0
0
0
0
0
0
0
D6
D6
D6
D6
D6
X
0
0
X
0
0
X
0
0
X
0
0
0
2
C EEPROM DIP switch
EEPROM 0
EEPROM 0
EEPROM 1
EEPROM 1
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
Data F
Data F
Data F
Data F
Data F
Data F
Data F
Data F
Data F
D5
D5
D5
D5
D5
0
0
0
0
EEPROM 0
EEPROM 0
EEPROM 1
EEPROM 1
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
Data E
Data E
Data E
Data E
Data E
Data E
Data E
Data E
Data E
5
D4
D4
D4
D4
D4
0
0
0
0
EEPROM 0
EEPROM 0
EEPROM 1
EEPROM 1
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
Data D
Data D
Data D
Data D
Data D
Data D
Data D
Data D
Data D
2
D3
D3
D3
D3
D3
C for 3.6 ms. If the part is addressed prior to this time,
0
0
0
0
DD
to the I
EEPROM 0
EEPROM 0
EEPROM 1
EEPROM 1
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
Data C
Data C
Data C
Data C
Data C
Data C
Data C
Data C
Data C
D2
D2
D2
D2
D2
2
0
0
0
0
C-bus is powered down or V
EEPROM 0
EEPROM 0
EEPROM 1
EEPROM 1
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
Data B
Data B
Data B
Data B
Data B
Data B
Data B
Data B
Data B
D1
D1
D1
D1
D1
0
0
0
0
PCA9561
Product data sheet
EEPROM 0
EEPROM 0
EEPROM 1
EEPROM 1
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
Data A
Data A
Data A
Data A
Data A
Data A
Data A
Data A
Data A
DD
D0
D0
D0
D0
D0
0
0
0
0
to the