pca9561 NXP Semiconductors, pca9561 Datasheet - Page 7

• Manufacturer Part Number: pca9561
• Description: Quad 6-bit Multiplexed I2c Eeprom Dip Switch
• Manufacturer: NXP Semiconductors

Philips Semiconductors
CHARACTERISTICS OF THE I
The I
(SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as control signals (see Figure 3).
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined
as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 4).
System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the
devices which are controlled by the master are the ‘slaves’ (see Figure 5).
2004 May 17
Quad 6-bit multiplexed I
SDA
SCL
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line
TRANSMITTER/
RECEIVER
MASTER
SDA
SCL
START condition
RECEIVER
SLAVE
2
S
C-BUS
SDA
SCL
2
Figure 4. Definition of start and stop conditions
C EEPROM DIP switch
TRANSMITTER/
Figure 5. System configuration
RECEIVER
SLAVE
data valid
data line
Figure 3. Bit transfer
stable;
7
change
allowed
of data
TRANSMITTER
MASTER
STOP condition
TRANSMITTER/
SW00363
RECEIVER
MASTER
P
SLAVE
SW00365
SDA
SCL
MULTIPLEXER
I
2
C
PCA9561
Product data sheet
SW00366