tda9950 NXP Semiconductors, tda9950 Datasheet - Page 5

• Manufacturer Part Number: tda9950
• Description: Tda9950 Cec/i?c-bus Translator
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Functional description
TDA9950_1
Product data sheet
8.1 Device addressing
8.2 Configuring the TDA9950
The TDA9950 uses an internal processor with embedded software to control the interface
between the CEC line and the I
The TDA9950 is a slave I
and protocol for the I
Table 4.
[1]
A1 and A0 are hardware-selectable pins.
In case of independent CEC, a system could have up to four TDA9950 devices on the
same I
The four addresses are defined by the state of the inputs A0 and A1 (logic 1 when
connected to V
The TDA9950 is controlled via a series of registers.
Table 5.
The first byte of any I
which determines the first TDA9950 register that will be read or written in the remainder of
the I
register, the register returned will be that to which the address pointer register was last
set.
The address pointer auto-increments after a successful read or write for all address
pointer values other than 00h. Auto-incremented addresses above 19h are invalid and
ignored.
Address code
Bit
Value
Register
APR
CSR
CER
CVR
CCR
ACKH
ACKL
CCONR
CDR
The Most Significant Bit (MSB), b7, is sent first.
2
C-bus transfer. If a read is carried out without a prior write to the address pointer
2
C-bus.
Device address code
I
2
C-bus register configuration
DD
Device code
b7
0
Description
Address Pointer Register
TDA9950 Status Register
TDA9950 Error Register
TDA9950 Version Register
TDA9950 Control Register
CEC Address ACK High register
CEC Address ACK Low register
CEC Configuration Register
CEC Data Registers
, logic 0 when connected to GND).
[1]
2
Rev. 01 — 16 November 2007
2
C-bus are standard.
C-bus write frame configures the address pointer register APR,
2
b6
1
C-bus device and the SCL pin is an input pin only. The timing
2
C-bus.
b5
1
b4
0
Address
00h
00h
01h
02h
03h
04h
05h
06h
07h - 19h
b3
1
Chip enable
b2
A1
CEC/I
TDA9950
© NXP B.V. 2007. All rights reserved.
2
b1
A0
C-bus translator
Read/Write
W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
b0
R/W
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