tda9955hl NXP Semiconductors, tda9955hl Datasheet
tda9955hl
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tda9955hl Summary of contents
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... Triple 8-bit analog-to-digital video converter for HDTV Rev. 01 — 17 March 2008 1. General description The TDA9955HL is a triple 8-bit video converter interface. The TDA9955HL converts an RGB analog signal into a RGB or YUV (YC signal or converts a YUV (YP with a sampling rate up to 170 MHz. The TDA9955HL supports analog TV resolutions from 480i (720 High-Defi ...
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... SYNC TIMING I C SLAVE MEASUREMENT INTERFACE SDA/SCL Rev. 01 — 17 March 2008 TDA9955HL 14 1.4 mm VPA[7:0] VPB[7:0] ADC VIDEO OUTPUT FORMATTER VPC[7: VCLK VREF, HREF, VHREF TIMING FREF GENERATOR VS, HS, CS TDA9955HL POWER MANAGEMENT 001aag612 Version SOT407-1 © NXP B.V. 2008. All rights reserved ...
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... Triple 8-bit analog-to-digital video converter for HDTV (GAIN (CLAMP (CLK PIX) (CLK FOR) TDA9955HL SYNC SDRS SELECTION Rev. 01 — 17 March 2008 TDA9955HL VHREF + TIMING GENERATOR + + + & POWER MANAGEMENT VPA[7:0] VPB[7:0] VPC[7:0] FREF ...
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... LOW analog supply for the free running oscillator (3 analog ground for the free running oscillator 22 P bias analog supply voltage (3 bias analog ground Rev. 01 — 17 March 2008 TDA9955HL 75 51 001aag613 © NXP B.V. 2008. All rights reserved ...
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... I reserved for test (connected to the digital ground of the core horizontal (composite) SYNC input horizontal (composite) SYNC input 2 Rev. 01 — 17 March 2008 TDA9955HL © NXP B.V. 2008. All rights reserved ...
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... O video port output bit video port output bit supply voltage for the video port output (3 ground for video port output 100 O video port C output bit 0 Rev. 01 — 17 March 2008 TDA9955HL © NXP B.V. 2008. All rights reserved ...
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... TDA9955HL_1 Product data sheet Triple 8-bit analog-to-digital video converter for HDTV 2 C-bus. An analog video input is defined by pins SOGx, Rx, Bx, Gx, and G/Y channels B Rev. 01 — 17 March 2008 TDA9955HL 2 C-bus and their content is validated only on © NXP B.V. 2008. All rights reserved ...
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... The sync multiplexer allow to select via the I pulses signals HS, VS, CS and DE. TDA9955HL_1 Product data sheet Triple 8-bit analog-to-digital video converter for HDTV , B/P and G/Y channels sampling and for C-bus the origin of the synchronization Rev. 01 — 17 March 2008 TDA9955HL © NXP B.V. 2008. All rights reserved ...
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... Oin C-bus, from the simple cut to the ITU-R BT.656 compliant 2 C-bus can replace the data stream during the Rev. 01 — 17 March 2008 TDA9955HL Oout 1 Oout + 2 Oout 3 © NXP B.V. 2008. All rights reserved. 2 C-bus ...
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... To assist the recognition of the input format, the vertical and horizontal periods are measured based on the externally provided MCLK frequency (13.5 MHz). The width of the horizontal pulse is also measured C-bus interface 2 9.1 I C-bus protocol The TDA9955HL is a slave I and protocol for I Bit A0 of the C-bus address is given in Table 3. Device address A6 ...
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Registers definitions The configuration of the registers is given in 2 Table 4. I C-bus registers; (R): reading register Register Sub R/W Bit definition addr 7 (MSB) VERSION 00h R 0 INPUT_SEL 01h W x Reserved for test 02h ...
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Table 4. I C-bus registers; (R): reading register Register Sub R/W Bit definition addr 7 (MSB) COARSE_GAINRV 20h W - FINE_GAINRV 21h W - AGC_HIGHRV 22h W AGC_LOWRV 23h W x COARSE_GAINBU 2Ah W - FINE_GAINBU 2Bh W - ...
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Table 4. I C-bus registers; (R): reading register Register Sub R/W Bit definition addr 7 (MSB) MAT_P21_MSB 8Dh W - MAT_P21_LSB 8Eh W MAT_P22_MSB 8Fh W - MAT_P22_LSB 90h W MAT_P23_MSB 91h W - MAT_P23_LSB 92h W MAT_P31_MSB 93h ...
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Table 4. I C-bus registers; (R): reading register Register Sub R/W Bit definition addr 7 (MSB) HS_MSB ABh W HS_E_LSB ACh W VREF_F1_S_MSB ADh W - VREF_F1_S_LSB AEh W VREF_F1_WIDTH AFh W VREF_F2_S_MSB B0h W - VREF_F2_S_LSB B1h W ...
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Table 4. I C-bus registers; (R): reading register Register Sub R/W Bit definition addr 7 (MSB) CLP_F2_LINE_S_LSB CFh W CLP_F2_LINE_WIDTH D0h W GAIN_S_LSB D1h W GAIN_MSB D2h W GAIN_E_LSB D3h W FDW_S_LSB D4h W FDW_MSB D5h W FDW_E_LSB D6h ...
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Table 4. I C-bus registers; (R): reading register Register Sub R/W Bit definition addr 7 (MSB) PD_AVI_CNTRL0 F4h W - PD_AVI_CNTRL1 F5h W - FVH_SEL F6h W - LSB_OUT_SEL F7h W OR_SEL F9h W x [1] The symbol ‘x’ ...
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... SDRS_FLAGS register (address 0Dh) bit description R additional sync pulses detected: additional sync pulses on the selected analog input 0* are not detected 1 are detected Rev. 01 — 17 March 2008 TDA9955HL video input 1 video input 2 enable disable enable disable enable disable [1] © ...
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... Symbol Access Value Description R reserved for test R - not used EDG R edge: synchronizes the PLL on the internal HSYNC pulses 0* on the rising edge 1 on the falling edge R reserved for test Rev. 01 — 17 March 2008 TDA9955HL [1] …continued © NXP B.V. 2008. All rights reserved ...
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... W 1 0000* phase: these bits set the phase shift for the three clock Rev. 01 — 17 March 2008 TDA9955HL master divider: selects the master divider to adjust the sampling frequency range with the PLL frequency range from 110 MHz to 200 MHz divided by 1; > 110 Msample/s divided by 2 ...
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... 10* 11 Rev. 01 — 17 March 2008 TDA9955HL output clock preset: these bits set the phase shift for the output clock CLKOUT the rough adjustment of the phase and there is the same number of steps as the division factor selected for CLKOUT formatter clock preset used to program the ...
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... Rev. 01 — 17 March 2008 TDA9955HL …continued phase delay: delays the rough adjustment of the three clock signals, see Table 15 no delay delay of one PLL period phase correction: selects the falling or rising edge of the horizontal reference signal from the PLL to ...
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... W W 5Ch* W F0h 90h* Rev. 01 — 17 March 2008 TDA9955HL …continued formatter clock selection: select the clock for the ITU-R656 formatter reserved for test CLKFOR not defined 0 for test: must be set to default value for proper operation brightness: these bits control the clamp level of ...
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... R 0000* R 00h* R 00* 00h* 00* Rev. 01 — 17 March 2008 TDA9955HL Description not used coarse_bu: coarse gain value for channel B/U not used fine_bu: fine gain value for channel B/U high_bu: AGC high value for channel B/U not used low_bu: AGC low value for channel B/U not used ...
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... W 0 0000* not used W 000* W 00h 0000* not used W 000* W 00h* W 00* Rev. 01 — 17 March 2008 TDA9955HL Description not used scale factor selection: fix the scale factor to convert the floating matrix [C ] into an integer matrix INT S ...
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... B W 69h 0000* not used 001* coefficient (3,3): coefficient from the B/C [2] B/C channel B W C0h Rev. 01 — 17 March 2008 TDA9955HL C input, 128 for B R channel to the R channel to the B channel to the R channel to the B channel to the R channel to the B ITU-R BT601 reduced scale conversion. ...
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... Symbol Access Value Description W 01h* W 0h* 0h* W 00h* Rev. 01 — 17 March 2008 TDA9955HL Description offset output 1: the new brightness values for the channel G/Y, e.g. with OFFSET_OUT1 = 0 0001 0000b = 10h offset output 2: the new brightness values for the channel R/V e.g. with YC C ...
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... Access Value Description W 00h* W 0h* W 0h* W 00h* Rev. 01 — 17 March 2008 TDA9955HL iVS in case of interlaced signal, line counter don’t care the iVS of second field rising edge of iVS loads the line counter with the LCNT_PR value 001aaa290 horizontal reference start: index of the first active pixel, and also the position of the rising edge of HREF signal and the position of SAV ...
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... Symbol Access Value Rev. 01 — 17 March 2008 TDA9955HL [1] Description 0 0000* not used 000* vertical reference start for field 1: index of the first blanking line for field 1, 00h* and also the position of the rising edge of VREF signal and the value of bit V in SAV/EAV code ...
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... HIGH during active video; LOW during horizontal blanking period HREF_END[11:0] Rev. 01 — 17 March 2008 TDA9955HL …continued Description 01h* vertical sync pixel start for field 1: position in number of pixels of the 0h* rising edge of the VS signal generated by the timing generator for fi ...
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... HREF_END[11:0] Symbol Access Value Description W FPOL Rev. 01 — 17 March 2008 TDA9955HL VREF VREF_F1_WIDTH[7:0] LOW during active video; HIGH during vertical blanking period VREF_F2 registers must be set to 0 VREF changes state at pixel 1 VREF_F1_START[10:0] VREF_F1_WIDTH[7:0] 00h* field reference for field 1 start (LSB): index of the fi ...
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... Symbol Access Value Description Symbol START[10:8] Rev. 01 — 17 March 2008 TDA9955HL FREF FREF_F1_START[10:0] LOW during field 1; HIGH during field 2 (can be changed with bit FIELD_POL) FREF_F2_START[10:0] 001aaa293 [1] 00h* clamp signal pixel start: position, in number of pixels, of the beginning of ...
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... GAIN_START pixels and can include the horizontal sync pulse. The gain Access Value Description W 00h* W 0h* W 0h* W 00h* Rev. 01 — 17 March 2008 TDA9955HL …continued Access Value Description W 0 not used 0000* 000* clamp signal line start for field 2 (LSB): position ...
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... DDh W 0* not used 10* blanking code bits 7 and 6 of the R/C see address DEh Rev. 01 — 17 March 2008 TDA9955HL interlaced detected: indicates an interlaced or progressive signal progressive interlaced automatic detection: the number of measured lines per frame correspond to 625 or 525 ( 2 lines of tolerance) ...
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... ACh* luminance ceiling level: fix the maximum code of the G/Y channel W not used 40h* luminance floor level: fix the minimum code of G/Y channel Rev. 01 — 17 March 2008 TDA9955HL and B/P channels for the YUV not used B/C downsampling filter: enables the shape of the B prefi ...
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... Rev. 01 — 17 March 2008 TDA9955HL output control: sets the outputs (VPA[11:0], VPB[11:0], VPC[11:0], VCLK, HS, VS, CS, HREF, VREF, FREF, DE, OR_R, OR_B, OR_G, CTL0 to CTL3, PL) outputs active outputs high-impedance video ports LOW forces the unused video port outputs to high-impedance ...
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... FREF; field reference signal 0* does not toggle; positive signal 1 toggles; negative signal Rev. 01 — 17 March 2008 TDA9955HL composite sync selection: selects the signal outputs on pin CS composite signal from the SDRS combination of HS and VS for test vertical sync selection: selects the signal outputs on ...
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... W horizontal reference selection: HREF dependence of VREF 0* 1 Rev. 01 — 17 March 2008 TDA9955HL …continued not used video port C selection: select the data stream to be output on video port C; see Table 48 video port B selection: select the data stream to be output on video port B; see ...
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... W software reset analog video interface: resets the digital clamp loop and the registers depending on the CLKPIX clock in manual mode 0* normal operation 1 reset mode W -* not used Rev. 01 — 17 March 2008 TDA9955HL …continued apx 3FF 000 000 EAV - apx 001aaa509 © NXP B.V. 2008. All rights reserved. ...
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... Power-down mode PD_AVI_CTRL1 register (address F5h) bit description Access Value Description W - not used power-down B/P blue channel (B/P 0* normal operation 1 Power-down mode Rev. 01 — 17 March 2008 TDA9955HL ADC: enables the power-down of the B ) ADC B © NXP B.V. 2008. All rights reserved ...
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... ADC output underflow or overflow of the range defined by the registers E1h and E2h 10 gain: monitors the gain calibration signal. see and Rev. 01 — 17 March 2008 TDA9955HL …continued ADC: enables the power-down of the R ) ADC R VPA[0]; VPB[0]; VPC[0] HREF; VREF; FREF ORGY ...
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... V pins supply voltage difference input voltage output current storage temperature ambient temperature junction temperature electrostatic discharge voltage human body model Thermal characteristics Parameter thermal resistance from junction to ambient Rev. 01 — 17 March 2008 TDA9955HL [1][2] …continued Figure 12 and Figure 13 Conditions Min Max 0.5 +4.6 0.5 +2 ...
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... Figure 9 sync pulse bi-level or tri-level horizontal sync pulse; 4 clock interval bi-level or tri-level horizontal sync pulse; 4 clock interval Rev. 01 — 17 March 2008 TDA9955HL = 1. 1. typical amb = V = 1.8 V and unless DDC(1V8) amb Min Typ 3 ...
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... RGB/YUV/YUV semi-planar/ITU-R BT.656 horizontal sync pulse delay; in phase with data outputs referenced to VCLK Rev. 01 — 17 March 2008 TDA9955HL = 1. 1. typical amb = V = 1.8 V and unless DDC(1V8) amb Min Typ - ...
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... V, V DDO(3V3) DDA(1V8) Conditions DDO 3 DDO SOG/Y 90% 10% Horizontal sync pulse on SOG/Y Rev. 01 — 17 March 2008 TDA9955HL = 1. 1. typical amb = V = 1.8 V and unless DDC(1V8) amb Min Typ = 2 mA mA; 2 ...
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... Rev. 01 — 17 March 2008 TDA9955HL YUV (ITU-R BT.656 ...
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... PL, MR input GND t PLH V OH TCU, TCD V M output V OL Rev. 01 — 17 March 2008 TDA9955HL U2n V2n Y4 Y2n Y2n 1 end of active line t PHL 001aag418 © NXP B.V. 2008. All rights reserved. ...
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... Triple 8-bit analog-to-digital video converter for HDTV 624 625 1st field 311 312 313 314 315 316 Rev. 01 — 17 March 2008 TDA9955HL 317 318 319 335 2nd field © NXP B.V. 2008. All rights reserved 336 mgw813 ...
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... Triple 8-bit analog-to-digital video converter for HDTV 522 523 524 525 261 262 263 264 265 266 2nd field Rev. 01 — 17 March 2008 TDA9955HL 1st field 267 268 279 280 © NXP B.V. 2008. All rights reserved. 18 281 001aah018 ...
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... scale (1) ( 0.27 0.20 14.1 14.1 16.25 16.25 0.5 0.17 0.09 13.9 13.9 15.75 15.75 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 17 March 2008 TDA9955HL detail 0.75 1.15 1 0.2 0.08 0.08 0.45 0.85 EUROPEAN PROJECTION SOT407 ( ...
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... Table 60. Revision history Document ID Release date TDA9955HL_1 20080317 TDA9955HL_1 Product data sheet Triple 8-bit analog-to-digital video converter for HDTV Data sheet status Change notice Product data sheet - Rev. 01 — 17 March 2008 TDA9955HL Supersedes - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 17 March 2008 TDA9955HL © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TDA9955HL All rights reserved. Date of release: 17 March 2008 Document identifier: TDA9955HL_1 ...