tda9955hl NXP Semiconductors, tda9955hl Datasheet - Page 28

• Manufacturer Part Number: tda9955hl
• Description: Triple 8-bit Analog-to-digital Video Converter For Hdtv
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 32.
Legend: * = default value
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Table 33.
Legend: * = default value
TDA9955HL_1
Product data sheet
Addr Register
ADh
AEh
AFh
B0h
B1h
B2h
Addr Register
B3h
B4h
B5h
B6h
B7h
B8h
In progressive case, bits VREF_F2_START[10:0] and VREF_F2_WIDTH[7:0] must be set to logic 0.
VREF_F1_S_MSB
VREF_F1_S_LSB
VREF_F1_WIDTH
VREF_F2_S_MSB
VREF_F2_S_LSB
VREF_F2_WIDTH
VS_F1_LINE_S_MSB 7 to 3 -
VS_F1_LINE_S_LSB
VS_F1_LINE_WIDTH 7 to 0 VS_F1_LINE_WIDTH[7:0]
VS_F2_LINE_S_MSB 7 to 3 -
VS_F2_LINE_S_LSB
VS_F2_LINE_WIDTH 7 to 0 VS_F2_LINE_WIDTH[7:0]
Vertical reference registers (address ADh to B2h) bit description
Vertical sync registers (address B3h to BEh) bit description
Bit
7 to 3 -
2 to 0 VREF_F1_START[10:8]
7 to 0 VREF_F1_START[7:0]
7 to 0 VREF_F1_WIDTH[7:0]
7 to 3 -
2 to 0 VREF_F2_START[10:8]
7 to 0 VREF_F2_START[7:0]
7 to 0 VREF_F2_WIDTH[7:0]
Bit
2 to 0 VS_F1_LINE_START[10:8] W
7 to 0 VS_F1_LINE_START[7:0]
2 to 0 VS_F2_LINE_START[10:8] W
7 to 0 VS_F2_LINE_START[7:0]
Symbol
Symbol
Rev. 01 — 17 March 2008
Triple 8-bit analog-to-digital video converter for HDTV
Access Value
W
W
W
W
W
W
W
W
Access Value
W
W
W
W
W
W
0 0000* not used
000*
00h*
00h*
0 0000* not used
000*
00h*
00h*
0 0000* not used
000*
00h*
00h*
0 0000* not used
000*
00h*
00h*
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Description
vertical reference start for field 1:
index of the first blanking line for field 1,
and also the position of the rising edge of
VREF signal and the value of bit V in
SAV/EAV code; if 0, VREF stays LOW
vertical reference width for field 1:
width of the vertical blanking for field 1,
and also the width of VREF signal and
the value of bit V in SAV/EAV code; if 0,
VREF stays LOW
vertical reference start for field 2:
index of the first blanking line for field 2,
and also the position of the rising edge of
VREF signal and the value of bit V in
SAV/EAV code
vertical reference width for field 2:
width of the vertical blanking for field 2,
and also the width of VREF signal and
the value of bit V in SAV/EAV code
Description
vertical sync line start for field 1:
position in number of lines of the VS
signal generated by the timing
generator for the field 1; if 0, VS
stays LOW
vertical sync line width for field
1: width in number of lines of the VS
signal generated by the timing
generator for field 1; if 0, VS stays
LOW
vertical sync line start for field 2:
position in number of lines of the VS
signal generated by the timing
generator for the field 2
vertical sync line width for field
2: width in number of lines of the VS
signal generated by the timing
generator for field 2
TDA9955HL
© NXP B.V. 2008. All rights reserved.
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