tda9150b NXP Semiconductors, tda9150b Datasheet - Page 7

• Manufacturer Part Number: tda9150b
• Description: Programmable Deflection Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2 Control bits.
July 1994
LFSS
DINT
BLDS
GBS
VAP
FBL
CSU
PRD
DIP
CPR
VPR
CONTROL BIT
Programmable deflection controller
LOGIC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Line stop: EW output current becomes zero and the vertical output current is reduced
to 20% of the adjusted value. LFSS becomes logic 0 after a HIGH on PON.
Line start enabled: the soft start mechanism is now activated.
De-interlace on: the V
De-interlace off: the V
edge is used as vertical reset.
Aquadag selected.
Bleeder selected.
Becomes logic 0 after power-on.
Guard band 48/12 lines.
Positive V
Negative V
Horizontal flyback slicing level = 3.9 V.
Horizontal flyback slicing level = 1.3 V.
No clamping suppression, standard mode of operation.
Clamping suppression in wait, stop and protection modes
(used in systems with e.g. TDA4680/81).
No defeat of HOUT, the over voltage information is only written in the PROT status bit.
HOUT is defeated and status bit PROT is set when over voltage is detected.
V
V
Nominal amplitude.
Compression to 75% of adjusted amplitude, used for display of 16 : 9 standard pictures
on 4 : 3 displays.
Nominal amplitude (100%) during wait, stop and clipping.
Amplitude reduced to 20% during wait, stop and clipping.
A
A
is sampled 42 clock pulses after the leading edge of H
is sampled 258 clock pulses after the leading edge of H
A
A
edge detection.
edge detection.
A
A
pulse is sampled at a position selected with control bit DIP.
pulse is sampled with the system clock and the detected rising
7
FUNCTION
A
.
A
.
Preliminary specification
TDA9150B