lm8328tmx National Semiconductor Corporation, lm8328tmx Datasheet - Page 26

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lm8328tmx

Manufacturer Part Number
lm8328tmx
Description
Mobile I/o Companion Supporting Keyscan, I/o Expansion Pwm, And Access.bus Host Interface
Manufacturer
National Semiconductor Corporation
Datasheet

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13.2.6 TIMIC - PWM Timer Interrupt Clear Register
Register - Name
Register - Name
Bit - Name
(reserved)
CYCIRQ2
CYCIRQ1
CYCIRQ0
CYCIRQ2
CYCIRQ1
CDIRQ2
CDIRQ1
CDIRQ0
CDIRQ2
CDIRQ1
CDIRQ0
TIMIC
Address
Address
0x7C
Bit
7:6
5
4
3
2
1
0
5
4
3
2
1
TABLE 37. TIMIC - PWM Timer Interrupt Clear Register
Default
Type
Type
0x0
0x0
0x0
0x0
0x0
0x0
W
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CDIRQ timer2.
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CDIRQ timer1.
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CDIRQ timer0.
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CYCIRQ timer2.
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CYCIRQ timer1.
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CYCIRQ timer0.
0: no interrupt pending
1: interrupt generated
This register clears timer and pattern interrupts.
CYCIRQ - Interrupt from the timers when PWM cycle is complete
(applies to the current PWM command residing in the active command
register of a PWM block).
CDIRQ - Interrupt from the pattern generator when PWM pattern code
is complete (applies to a completed task residing in the script buffer
of a PWM block)
(reserved)
Clears interrupt CDIRQ timer2.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer1.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer0.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer2.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer1.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
26
Register Function
Register Function
Bit Function

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