adv7180 Analog Devices, Inc., adv7180 Datasheet - Page 13

• Manufacturer Part Number: adv7180
• Description: 10-bit, 4 X Oversampling Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

64-LEAD LQFP
Table 9. Pin Function Description for the ADV7180 LQFP-64
Pin No.
3, 10, 24, 57
32, 37, 43
4, 11
23, 58
40
31
38
39
35, 36, 46 to 49
27, 28, 33, 41, 42,
44, 45, 50
5 to 8, 14 to 19,
25, 26, 59 to 62
2
64
63
1
53
54
52
29
30
51
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
VREFP
VREFN
A
NC
P11 to P8,
P7 to P2, P1,
P0, P15 to P12
HS
VS
FIELD
INTRQ
SDATA
SCLK
ALSB
PWRDWN
ELPF
RESET
IN
1 to A
IN
6
DVDDIO
DVDDIO
NC = NO CONNECT
INTRQ
DGND
DGND
GPO1
GPO0
Type
G
G
P
P
P
P
O
O
I
O
O
O
O
O
I/O
I
I
I
I
I
SFL
P11
P10
HS
P9
P8
P7
P6
P5
10
11
12
13
14
15
16
1
3
9
2
4
5
6
7
8
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
Analog Video Input Channels.
No Connect Pins. These pins are not connected internally.
Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes.
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
I
I
This pin selects the I
selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42.
A logic low on this pin places the ADV7180 in power-down mode.
The recommended external loop filter must be connected to the ELPF pin, as shown in
Figure 54.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
2
2
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
Figure 8. 64-Lead LQFP Pin Configuration
Rev. B | Page 13 of 112
(Not to Scale)
ADV7180
TOP VIEW
LQFP
2
C address for the ADV7180. For ALSB set to Logic 0, the address
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A
A
A
NC
NC
AGND
NC
NC
AVDD
VREFN
VREFP
AGND
A
A
TEST_0
NC
IN
IN
IN
IN
IN
5
4
3
2
1
ADV7180