adv7180 Analog Devices, Inc., adv7180 Datasheet - Page 48

• Manufacturer Part Number: adv7180
• Description: 10-bit, 4 X Oversampling Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

ADV7180
Table 62. User Settings for PAL
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
PVBEGDELO, PAL Vsync Begin Delay on Odd Field,
Address 0xE8 [7]
When PVBEGDELO is 0 (default), there is no delay.
Setting PVBEGDELO to 1 delays vsync going high on an odd
field by a line relative to PVBEG.
PVBEGDELE PAL, Vsync Begin Delay on Even Field,
Address 0xE8 [6]
When PVBEGDELE is 0, there is no delay.
Setting PVBEGDELE to 1 (default) delays vsync going high on
an even field by a line relative to PVBEG.
PVBEGSIGN PAL, Vsync Begin Sign, Address 0xE8 [5]
Setting PVBEGSIGN to 0 delays the beginning of vsync. Set for
user manual programming.
Setting PVBEGSIGN to 1(default) advances the beginning of
vsync. Not recommended for user programming.
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
VIDEO
VIDEO
FIELD
FIELD
HS
HS
VS
VS
622
310
Register Name
VS/FIELD Control 1
VS/FIELD Control 2
VS/FIELD Control 3
HS Position Control 1
HS Position Control 2
HS Position Control 3
Polarity
PAL V Bit Begin
PAL V Bit End
PAL F Bit Toggle
311
623
624
312
Figure 39. PAL Typical VS/FIELD Positions Using Register Writes Shown in Table 62
625
313
FIELD 1
1
FIELD 2
314
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
315
2
PVBEG[4:0] = 0x1
PVBEG[4:0] = 0x1
3
316
Rev. B | Page 48 of 112
317
4
5
318
PVEND[4:0] = 0x4
PVBEG[4:0], PAL Vsync Begin, Address 0xE8 [4:0]
The default value of PVBEG is 00101, indicating the PAL vsync
begin position. For all NTSC/PAL vsync timing controls, the
V bit in the AV code and the vsync on the VS pin are modified.
PVEND[4:0] = 0x4
319
6
NOT VALID FOR USER
PROGRAMMING
7
320
VSYNC BY PVBEG[4:0]
ADVANCE BEGIN OF
ADVANCE BY
PVBEGDELO
ADDITIONAL
321
8
DELAY BY
PFTOG[4:0] = 0x6
0.5 LINE
VSBHO
1 LINE
YES
PFTOG[4:0] = 0x6
1
1
Figure 40. PAL Vsync Begin
322
9
1
323
10
VSYNC BEGIN
0
0
PVBEGSIGN
ODD FIELD?
11
336
0
0
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
337
23
ADVANCE BY
PVBEGDELE
ADDITIONAL
DELAY BY
0
0.5 LINE
VSBHE
1 LINE
NO
1
1
24