ADV7150LS135 AD [Analog Devices], ADV7150LS135 Datasheet
ADV7150LS135
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ADV7150LS135 Summary of contents
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FEATURES 220 MHz, 24-Bit (30-Bit Gamma Corrected) True Color Triple 10-Bit “Gamma Correcting” D/A Converters Triple 256 10 (256 30) Color Palette RAM On-Chip Clock Control Circuit Palette Priority Select Registers RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs ...
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ADV7150–SPECIFICATIONS pF); IOR, IOG, IOB = GND. All specifications T L Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS (Excluding CLOCK, CLOCK) Input High Voltage, V ...
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TIMING CHARACTERISTICS IOR, IOG, I0B = GND. All specifications T MIN CLOCK CONTROL AND PIXEL PORT 220 MHz 170 MHz 135 MHz 110 MHz 85 MHz Parameter Version Version f 220 170 CLOCK t 4.55 5. 2.5 ...
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ADV7150 NOTES 1 TTL input values are volts, with input rise/fall times V –0 –1.8 V, with input rise/fall times AA AA puts. Analog output load 10 pF. Databus (D0–D9) loaded as shown in ...
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CLOCK LOADOUT LOADIN PIXEL INPUT N+1 N DATA N+1 N+1 IOR, IOR ANALOG IOG, IOG OUTPUT A B N–1 N–1 IOB, IOB DATA I PLL, SYNCOUT t PD ...
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ADV7150 CLOCK LOADOUT LOADIN PIXEL INPUT N+1 N DATA* IOR, IOR ANALOG IOG, IOG OUTPUT IOB, IOB DATA I PLL, SYNCOUT *INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC Figure ...
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CLOCK PRGCKOUT (CLOCK/4) PRGCKOUT (CLOCK/8) PRGCKOUT (CLOCK/16) PRGCKOUT (CLOCK/32 Figure 8. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT SCKIN t 15 BLANK SCKOUT END OF SCAN LINE (N) Figure 9. Video Data Shift Clock Input ...
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... ORDERING GUIDE Speed 220 MHz ADV7150LS220 110 MHz ADV7150LS110 170 MHz ADV7150LS170 85 MHz 135 MHz ADV7150LS135 NOTES 1 ADV7150 is packaged in a 160-pin plastic quad flatpack, QFP. 2 All devices are specified for +70 C operation. 3 Contact sales office for latest information on package design. t ...
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Pin Pin Number Mnemonic Number ...
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ADV7150 Mnemonic RED ( – GREEN ( – BLUE ( ...
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Mnemonic R/W C0, C1 IOR; IOR, IOG; IOG, IOB; IOB V REF R SET COMP I PLL V AA GND REV. A Function Read/Write Control (TTL Compatible Input). This input determines whether data is written to or read from the ...
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ADV7150 The device consists of three, high speed, 10-bit, video D/A con- verters (RGB), three 256 10 (one 256 tables, palette priority selects, a pixel input data multiplexer/ serializer and a clock generator/divider circuit. The ADV7150 is capable of 1:1, ...
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Color data is latched into the parts pixel port on every rising edge of LOADIN (see Timing Waveform, Figure 3). The required frequency of LOADIN is determined by the multiplex rate, where 4:1 Multiplex Mode LOADIN ...
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ADV7150 CLOCK, CLOCK Inputs The Clock Control Circuit is driven by the pixel clock inputs, CLOCK and CLOCK. These inputs can be driven by a differ- ential ECL oscillator running from supply. Alternatively, the ADV7150 CLOCK inputs ...
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Pipeline Delay and Onboard Calibration The ADV7150 has a fixed number of pipeline delays (t long as timings t and -t are met. However fixed pipeline 10 11 delay is not a requirement, timings t and -t 10 ...
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ADV7150 15-Bit “Gamma” True Color (CR24, CR25, CR26, CR27 = and MR11 = 1) The part is set to 15-bit True-Color operation. The pixel port accepts 15-bits of color data which ...
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ADV7150 ADDRESS MODE REGISTER REGISTER ADDR (A7–A0) (MR1 R/W Data is read from the color palette by first writing to the address register of the color palette location to be read. The MPU per- forms three successive read ...
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Table III. Interface Truth Table (10-Bit Databus Mode) R Databus (D9–D0 DB7–DB0 DB7–DB0 DB7–DB0 DB9–DB0 DB9–DB0 DB9–DB0 ...
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ADV7150 Power-On Reset On power-up of the ADV7150 executes a power-on reset opera- tion. This initializes the pixel port such that the pixel sequence ABCD starts at A. The Mode Register (MR17–MR10), Com- mand Register 2 (CR27–CR20) and Command Register ...
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Palette Select Match Bits Control (MR17–MR16) These bits allow multiple palette devices to work together. When bits PS1 and PS0 match MR17 and MR16 respectively, the device is selected. If these bits do not match, the device is not selected ...
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ADV7150 COMMAND REGISTER 2 (CR2) (Address Reg (A7–A0) = 06H) This register contains a number of control bits as shown in the diagram. CR2 is a 10-bit wide register. However, for program- ming purposes, it may be considered as an ...
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COMMAND REGISTER 3 (CR3) (Address Reg (A7–A0) = 07H) This register contains a number of control bits as shown in the diagram. CR3 is a 10-bit wide register. However for program- ming purposes, it may be considered as an 8-bit ...
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ADV7150 DIGITAL-TO-ANALOG CONVERTERS (DACS) AND VIDEO OUTPUTS The ADV7150 contains three high speed video DACs. The DAC outputs are represented as the three primary analog color signals IOR (red video), IOG (green video) and IOB (blue video). Other analog signals ...
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IOR, IOB IOG 18.62 0.698 26.67 1.000 100 IRE 0 0 8.05 0.302 43 IRE 0 0 Figure 31. Composite Video Waveform SYNC IOR, IOB, IOG mA V 19.05 0.714 92.5 IRE 0.054 1.44 7.5 IRE ...
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ADV7150 BOARD DESIGN AND LAYOUT CONSIDERATIONS + 0 COMP ADV7150 GND The ADV7150 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference ...
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Digital Signal Interconnect The digital inputs to the ADV7150 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock ...
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ADV7150 10-Bit DACs 10-Bit RAM-DAC resolution allows for nonlinear video correc- tion, in particular Gamma Correction. The ADV7150 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. ...
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Palette Priority Select Inputs The palette priority selection inputs allow up to four separate palette devices to be used in a single system to drive a single monitor with subpixel resolution. The IOR, IOG and IOB ana- log video output ...
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ADV7150 ADV7150 Initialization After power has been supplied, the ADV7150 must be initial- ized. The Mode Register and Control Registers must be set. The values written to the various registers will be determined by the desired operating mode of the ...
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Example 2 Color Mode 24-Bit Gamma Corrected True Color (30 Bits) Multiplexing 2:1 Databus 10 Bit RAM-DAC Resolution 10 Bit SYNC Ignored Pedestal 0 IRE Calibration Every Vertical Sync Register Initialization Write 0FH to Mode Register (MR1) Write 0EH to ...
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ADV7150 SYNC BLANK GRAPHICS PIPELINE PIXEL INPUT DATA MUX TRIGGER DECODE The ADV7150 contains onboard circuitry which enables both device and system level test diagnostics. The test circuitry can be used to test the frame buffer memory as well as ...
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THERMAL AND ENVIRONMENTAL CONSIDERATIONS The ADV7150 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and environmental conditions in which the ADV7150 must operate. Reliability ...
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ADV7150 0.037 (0.95) 0.026 (0.65) 0.004 (0.10) APPENDIX 8 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). S-160 160-Lead Plastic Power Quad Flatpack 1.239 (31.45) 1.219 (30.95) 0.160 (4.07) 1.107 (28.10) MAX 1.100 (27.90 120 121 4 4 ...
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–35– ...
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REV. A ...