x9440 Intersil Corporation, x9440 Datasheet - Page 5

• Manufacturer Part Number: x9440
• Description: Mixed Signal With Spi Interface
• Manufacturer: Intersil Corporation

REGISTER BIT DESCRIPTIONS
Wiper Counter Register (WCR)
WP0-WP5 identify wiper position.
Analog Control Register (ACR)
Shutdown
“1”
“0”
Enable
“1”
“0”
Latch
“1”
“0”
Userbits—available for user applications
Data Registers (DR, R
{Refer to Memory Map, Figure 9}
INSTRUCTIONS AND PROGRAMMING
Identification (ID) Byte
The first byte sent to the X9440 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9440 this
is fixed as 0101[B] (refer to Figure 2).
0 0
0
Wiper Position or Analog Control Data or User Data
indicates power is connected to the voltage
comparator.
indicates power is not connected to the voltage
comparator.
indicates the output buffer of the voltage
comparator is enabled.
indicates the output buffer of the voltage
comparator is disabled.
indicates the output of the voltage comparator is
memorized or latched.
indicates the output of the voltage comparator is
not latched.
User-
0
bit5
WP5 WP4 WP3 WP2 WP1
(volatile)
User-
bit4
(volatile)
(Nonvolatile)
User-
bit3
0
-R
3
5
)
Latch Enable
down
Shut-
(LSB)
(LSB)
WP0
X9440
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
The X9440 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9440 to successfully
continue the command sequence. The A
can be actively driven by CMOS input signals or tied to
V
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots or two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 3.
Figure 3. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R
of the four data registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P
ometers is to be affected by the instruction.
The four high order bits define the instruction. The next
two bits (R
that is to be acted upon when a register oriented instruc-
tion is issued. The last two bits (P
one of the two potentiometers or which one of the two
voltage comparators is to be affected by the instruction.
CC
or V
1
and P
SS
0
I3
1
.
Device Type
and R
Instructions
Identifier
1
I2
0
) selects which one of the four potenti-
0
) select one of the four data registers
0
I1
1
I0
0
R1
Register
Select
1
0
R0
1
and P
Device Address
and R
A1
Pot Select
0
P1
-A
0
) select which
0
1
) select one
0
A0
input pins.
-A
P0
March 28, 2005
1
FN8200.0
inputs