x9440 Intersil Corporation, x9440 Datasheet - Page 7

• Manufacturer Part Number: x9440
• Description: Mixed Signal With Spi Interface
• Manufacturer: Intersil Corporation

Figure 6. Three-Byte Command Sequence (Read)
Figure 7. Increment/Decrement Command Sequence
Increment/Decrement
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (t
while SI is HIGH, the selected wiper will move one
resistor segment towards the V
each SCK clock pulse while SI is LOW, the selected
Figure 8. Increment/Decrement Timing Limits
SCK
SCL
CS
CS
SI
S0
SI
0
0
1
SCK
1
V
SI
W
0
0
1
7
1
INC/DEC CMD Issued
0
H
0
0
terminal. Similarly, for
0
A1 A0
A1 A0
I3
Voltage Out
HIGH
I2
I3
)
I2
I1 I0
X9440
I1
R1 R0 P1 P0
I0
wiper will move one resistor segment towards the V
terminal. A detailed illustration of the sequence and tim-
ing for this operation are shown in Figure 7 and 8.
Write in Process
The contents of the data registers are saved to nonvol-
atile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.
0
0
P1 P0
t
WRID
0
0
N
C
1
Don’t Care
I
D5 D4 D3 D2 D1 D0
N
C
2
I
N
C
n
I
D
E
C
1
March 28, 2005
D
E
C
n
FN8200.0
L