dac1005d650 NXP Semiconductors, dac1005d650 Datasheet - Page 21

• Manufacturer Part Number: dac1005d650
• Description: Dual 10-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1005D650_1
Product data sheet
10.3.1 Dual-port mode
10.3.2 Interleaved mode
10.3 Input data
Table 28.
Table 29.
Default settings are shown highlighted.
The setting applied to MODE_SEL (register 00h[3]; see
whether the DAC1005D650 operates in the Dual-port mode or in the Interleaved mode
(see
Table 30.
The data input for Dual-port mode operation is shown in
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
The data input for Interleaved mode operation is shown in
operation”.
Bit
7 to 0
Bit
7
1 to 0
Bit 3 setting
0
1
Fig 5.
Table
Symbol
AUX_B[9:2]
Symbol
AUX_B_PD
AUX_B[1:0]
n in Qn = 0 to 9 and for In is 0 to 9.
Dual-port mode
DAC_B_Aux_MSB register (address 1Ch) bit description
DAC_B_Aux_LSB register (address 1Dh) bit description
Mode selection
30).
Function
Dual-port mode (pin Q9)
Interleaved mode (pin SELIQ) active
Qn
In
Access
R/W
Rev. 01 — 28 July 2009
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
LATCH
LATCH
Q
I
Value
-
Access Value
R/W
R/W
2
2
FIR 1
FIR 1
Description
most significant 8 bits for the auxiliary DAC B
0
1
I9 to I0
active
2
2
FIR 2
FIR 2
Description
auxiliary DAC B power
lower 2 bits for the auxiliary DAC B
on
off
Table 10 on page
Figure 5 “Dual-port
Figure 6 “Interleaved mode
DAC1005D650
2
2
FIR 3
FIR 3
001aaj585
Q9 to Q0
active
off
© NXP B.V. 2009. All rights reserved.
17) defines
mode”. Each
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