dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 17

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dac1408d650

Manufacturer Part Number
dac1408d650
Description
Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
dac1408d650HN/C1:5
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NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.2.3 K detect & word align
The SYNC signal is also used during normal operation by the DAC1408D650 to request a
link re-initialization. This occurs when the 8b/10b module loses synchronization.
The SYNC_OUT signal conforms to LVDS signaling. Its common mode voltage (see
39 “Page 2 register allocation
39 “Page 2 register allocation
SYNC_OUT is synchronous with the frame clock.
Table 7.
[1]
This stage monitors the datastream for code-characters (komma-detect), decodes the
words to bytes (octets) and performs optional character-replacement as part of frame/lane
alignment monitoring and correction. This module will provide the required control signals
to the RX-controller and ILA.
This module decodes the 10 bit words into 8 bit words (octets). The decode table is
specified in the IEEE Std.802.3-2005 specification (page 41 Table 36 -1a). During
decoding, the disparity is calculated according to the disparity rules mentioned in the
same specification IEEE Std.802.3-2005 (page 39 chapter 36.2.4.4). When the disparity
counter is more than 2 or less than 2, an error will be generated.
The following comma symbols are detected during data transmission irrespective of the
running disparity:
The following flags are also triggered according to the following definitions:
Symbol Parameter
t
A flag is sent to the control interface to reflect detected commas in registers.
d
Fig 7.
C = guaranteed by characterization.
SYNC_OUT timing
delay time
SYNC_OUT timing
/K/=K28.5
/F/=K28.7
/A/=K28.3
/R/=K28.0
/Q/=K28.4
Conditions
frame clock to sync
Rev. 01 — 26 May 2009
SYNC_OUT
t
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
FS_R(min)
map”) and its differential peak to peak amplitude (see
map”) can be programmed via registers.
CLK
t
FS_R(max)
Test
C
[1]
Min
tbd
001aak165
DAC1408D650
Typ
-
© NXP B.V. 2009. All rights reserved.
Max
tbd
Unit
ns
17 of 88
Table
Table

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