dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 63

• Manufacturer Part Number: dac1408d650
• Description: Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.15.2.8 Page 5 bit definition detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 95.
Default settings are shown highlighted.
Table 96.
Default settings are shown highlighted.
Table 97.
Default settings are shown highlighted.
Table 98.
Default settings are shown highlighted.
Bit
7 to 4 ILA_MON_LN1[3:0]
3 to 0 ILA_MON_LN0[3:0]
Bit
7 to 4 ILA_MON_LN3[3:0]
3 to 0 ILA_MON_LN2[3:0]
Bit
3
2
1
0
Bit
7 to 6 CA_MON_LN3[1:0]
5 to 4 CA_MON_LN2[1:0]
3 to 2 CA_MON_LN1[1:0]
1 to 0 CA_MON_LN0[1:0]
Symbol
Symbol
Symbol
ILA_BUF_ERR_LN3
ILA_BUF_ERR_LN2
ILA_BUF_ERR_LN1
ILA_BUF_ERR_LN0
Symbol
ILA_MON_1_0 register (address 00h) bit description
ILA_MON_3_2 register (address 01h) bit description
ILA_BUF_ERR register (address 02h) bit description
CA_MON register (address 03h) bit description
Table 94
Rev. 01 — 26 May 2009
for a register overview and their default values. In the following
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
R/W
R/W
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Access Value Description
R/W
R/W
Value Description
0
1
0
1
0
1
0
1
Value Description
ila_buf_ln1 pointer
ila_buf_ln0 pointer
ila_buf_ln3 pointer
ila_buf_ln2 pointer
clock alignment phase monitor lane_3
clock alignment phase monitor lane_2
clock alignment phase monitor lane_1
clock alignment phase monitor lane_0
ila_buf_ln3 pointer is in range
ila_buf_ln3 pointer is out of range
ila_buf_ln2 pointer is in range
ila_buf_ln2 pointer is out of range
ila_buf_ln1 pointer is in range
ila_buf_ln1 pointer is out of range
ila_buf_ln0 pointer is in range
ila_buf_ln0 pointer is out of range
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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