adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 31

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 27. Serial Ports—External Clock
1
2
Table 28. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
Referenced to the sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DFSIR
HOFSIR
DDTI
HDTI
SCLKIW
1
1
1
1
2
2
2
1
1
2
1
2
2
1
2
2
2
2
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. D | Page 31 of 56 | April 2008
Serial port signals (SCLK, FS, data channel A, data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Min
2.5
2.5
2.5
2.5
12
24
2
2
Min
7
2.5
7
2.5
–1.0
–1.0
–1.0
0.5t
K and B Grade
SCLK
K and B Grade
– 2
Max
9.5
9.5
Max
3
8
3
0.5t
SCLK
Max
11
11
+ 2
Y Grade
Max
3.5
9.5
4.0
0.5t
Y Grade
SCLK
+ 2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns