adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 40

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver. This feature is not available on the
ADSP-21363 models.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)
1
Parameter
Switching Characteristics
t
t
t
t
t
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
(DATA CHANNEL A/B)
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing
(SCLK)
(FS)
DRIVE EDGE
Rev. D | Page 40 of 56 | April 2008
t
t
HOFSI
HDTI
t
DFSI
t
SCLKIW
t
DDTI
Min
–2
–2
38
SAMPLE EDGE
Max
5
5
Unit
ns
ns
ns
ns
ns