adsp-2191m Analog Devices, Inc., adsp-2191m Datasheet - Page 23
adsp-2191m
Manufacturer Part Number
adsp-2191m
Description
Dsp Microcomputer
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-2191M.pdf
(48 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
adsp-2191mBCA-140
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
adsp-2191mBCAZ-140
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
adsp-2191mBST-140
Manufacturer:
AD
Quantity:
1 831
Part Number:
adsp-2191mBST-140
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
adsp-2191mBSTZ-140
Manufacturer:
MAXIM
Quantity:
101
Company:
Part Number:
adsp-2191mBSTZ-140
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
adsp-2191mKCA-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
adsp-2191mKCA-160
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
adsp-2191mKCAZ-160
Manufacturer:
ADI
Quantity:
166
Company:
Part Number:
adsp-2191mKSTZ-160
Manufacturer:
AD
Quantity:
1 000
Part Number:
adsp-2191mKSTZ-160
Manufacturer:
ADI/亚德诺
Quantity:
20 000
External Port Read Cycle Timing
Table 13
For additional information on the ACK signal, see the discussion
on Page
Table 13. External Port Read Cycle Timing
1
2
3
REV. A
t
These are timing parameters that are based on worst-case operating conditions.
W = (number of waitstates specified in wait register)
HCLK
Parameter
Switching Characteristics
t
t
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
CSRS
ARS
RSCS
RW
RSA
RWR
AKW
RDA
ADA
SDA
SD
HRD
DRSAK
is the peripheral clock period.
22.
and
1, 2
Figure 12
MS3--0
A21–0
D15–0
IOMS
BMS
ACK
WR
RD
Chip Select Asserted to RD Asserted Delay
Address Valid to RD Setup and Delay
RD Deasserted to Chip Select Deasserted Setup
RD Strobe Pulsewidth
RD Deasserted to Address Invalid Setup
RD Deasserted to WR, RD Asserted
ACK Strobe Pulsewidth
RD Asserted to Data Access Setup
Address Valid to Data Access Setup
Chip Select Asserted to Data Access Setup
Data Valid to RD Deasserted Setup
RD Deasserted to Data Invalid Hold
ACK Delay from RD Low
describe external port read operations.
t
CSRS
t
Figure 12. External Port Read Cycle Timing
ARS
t
HCLK
t
DRSAK
.
t
CDA
t
t
t
RDA
ADA
SDA
t
AKW
–23–
t
RW
t
S D
Min
0.5t
0.5t
0.5t
t
0.5t
t
t
7
0
0
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
–2+W
–3
–3
–2
–2
t
t
RWR
H R D
t
t
RSA
3
RSCS
Max
t
t
t
ADSP-2191M
HCLK
HCLK
HCLK
–4+W
+W
+W
3
3
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns