adsp-2191m Analog Devices, Inc., adsp-2191m Datasheet - Page 40

• Manufacturer Part Number: adsp-2191m
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2191M
Output Drive Currents
Figure 25
of the ADSP-2191M. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
Table 23. P
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
Where:
• P
• P
Pin Type
Address
MSx
WR
Data
CLKOUT
in
EXT
INT
Power Dissipation on Page
–100
–20
–40
–60
–80
is I
is from
60
40
20
0
shows typical I-V characteristics for the output drivers
0
DDINT
Figure 25. Typical Drive Currents
EXT
0.5
# of Pins
15
1
1
16
1
Table 23
Calculation Example
P
OUTPUT CURRENT
2.5 V, using the calculation I
TOTAL
1.0
SOURCE (V
INPUT CURRENT
1.5
=
V
V
DDEXT
OL
DDEXT
P
EXT
% Switching
50
0
—
50
—
2.0
) VOLTAGE – V
19.
= 3.65V @
+
V
V
V
V
DDEXT
DDEXT
DDEXT
DDEXT
2.5
P
V
DDEXT
INT
– 40°C
= 3.0V @
= 3.0V @
= 3.3V @
= 3.65V @
= 3.3V @
3.0
V
OH
3.5
+ 85°C
+ 85°C
+ 25°C
DDINT
– 40°C
+ 25°C
10 pF
10 pF
10 pF
10 pF
10 pF
4.0
C
listed
–40–
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• Number of output pins that switch during each cycle (O)
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
• Their voltage swing (V
and is calculated by the formula below.
The load capacitance includes the processor’s package capaci-
tance (C
high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2t
every cycle at a frequency of 1/t
but selects can switch on each cycle. For example, estimate P
with the following assumptions:
• A system with one bank of external data memory—asyn-
• One 64K 16 RAM chip is used with a load of 10 pF
• Maximum peripheral speed CCLK = 80 MHz, HCLK =
• External data memory writes occur every other cycle, a
• The bus cycle time is 80 MHz (t
The P
drive as shown in
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by –V is dependent on the capacitive load, C
load current, I
equation below.
chronous RAM (16-bit)
80 MHz
rate of 1/(4t
20 MHz
20 MHz
40 MHz
20 MHz
80 MHz
f
EXT
IN
equation is calculated for each class of pins that can
). The switching frequency includes driving the load
L
HCLK
. This decay time can be approximated by the
Table
P
EXT
), with 50% of the pins switching
23.
=
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
DD
VDD2
O C
)
×
CK
CK
. Select pins switch at 1/(2t
). The write strobe can switch
INT
×
V
. Maximum P
HCLK
DD
2
= P
= 0.01635 W
= 0.0 W
= 0.00436 W
= 0.01744 W
= 0.00872 W
P
×
EXT
= 12.5 ns)
f
EXT
=0.04687 W
EXT
INT
are different
L
cannot
and the
REV. A
CK
EXT
),