adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 22

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
Power-Up Sequencing
The timing requirements for processor startup are given in
Table
between V
system designs should take into account.
Table 14. Power Up Sequencing Timing Requirements (Processor Startup)
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
Based on CLKIN cycles.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
cycles maximum.
• No power supply should be powered up for an extended
• If the V
period of time (> 200 ms) before another supply starts to
ramp up.
such as RESETOUT and RESET may actually drive
momentarily until the V
14. While no specific power-up sequencing is required
1
DD
_
INT
DD
and V
DD
_
EXT
_
INT
and V
DD
CLK_CFG1–0
power supply comes up after V
_
RESETOUT
EXT
RESET
V
V
CLKIN
DDINT
DDEXT
assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary
DD
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
_
INT
DD
_
, there are some considerations that
INT
SRST
DD
On Before V
_
INT
specification in
rail has powered up. Systems
t
RSTVDD
DD
DD
DD
_
_
Table
EXT
_
INT
EXT
and V
DD
or V
16. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
t
IVDDEVDD
Rev. PrA | Page 22 of 66 | March 2010
_
EXT
DD
Figure 5. Power-Up Sequencing
DD
, any pin,
_
_
INT
EXT
On
Valid
t
CLKVDD
t
PLLRST
t
CLKRST
Note that during power-up, when the V
comes up after V
state leakage current pull-up, pull-down, may be observed on
any pin, even if that is an input only (for example the RESET
pin) until the V
sharing these signals on the board must determine if there
are any issues that need to be addressed based on this
behavior.
DD
Min
0
–200
0
10
20
4096 × t
DD
Preliminary Technical Data
_
INT
2
3
_
t
CORERST
EXT
rail has powered up.
, a leakage current of the order of three-
CK
+ 2 × t
CCLK
4, 5
DD
_
INT
Max
+200
200
power supply
Unit
ms
ms
ms
ms
ms
ms