adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 41

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Sample Rate Converter—Serial Input Port
The ASRC input signals are routed from the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided in
Table 36
Table 36. ASRC, Serial Input Port
1
Parameter
Timing Requirements
t
t
t
t
t
t
The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
SRCSFS
SRCHFS
SRCSD
SRCHD
SRCCLKW
SRCCLK
be either CLKIN or any of the DAI pins.
1
1
1
1
are valid at the DAI_P20–1 pins.
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Clock Width
Clock Period
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
Figure 27. ASRC Serial Input Port Timing
Rev. PrA | Page 41 of 66 | March 2010
t
SRCCLKW
t
SRCSD
t
SRCSFS
SAMPLE EDGE
ADSP-21483/21486/21487/21488/21489
t
t
SRCHFS
SRCHD
t
SRCCLK
Min
4
5.5
4
5.5
(t
t
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
Unit
ns
ns
ns
ns
ns
ns