adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 44

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 30
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed 12-bit clock peri-
ods (in 20-bit output mode) or 16-bit clock periods (in 16-bit
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
LRCLK
SDATA
SCLK
SDATA
LRCLK
SDATA
LRCLK
SCLK
SCLK
shows the right-justified mode. LRCLK is high for the
2
S, or right justified with word widths of 16-, 18-,
LSB
MSB
MSB – 1
MSB
MSB – 2
MSB – 1
MSB – 2
LSB + 2
MSB
LEFT CHANNEL
MSB – 1
LEFT CHANNEL
LSB + 1
LSB + 2
MSB – 2
LEFT CHANNEL
LSB + 1
LSB
Rev. PrA | Page 44 of 66 | March 2010
LSB
Figure 30. Right-Justified Mode
Figure 32. Left-Justified Mode
LSB + 2
Figure 31. I
LSB + 1
LSB
MSB
2
MSB – 1
S Mode
RIGHT CHANNEL
MSB
output mode) from an LRCLK transition, so that when there are
64 Serial clock periods per LRCLK period, the LSB of the data
will be right-justified to the next LRCLK transition.
Figure 31
channel and high for the right channel. Data is valid on the ris-
ing edge of serial clock. The MSB is left-justified to an LRCLK
transition but with a single Serial Clock period delay.
Figure 32
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no MSB delay.
MSB – 2
MSB – 1
MSB – 2
shows the default I
shows the left-justified mode. LRCLK is high for the
RIGHT CHANNEL
RIGHT CHANNEL
LSB + 2
MSB
MSB – 1
LSB + 1
Preliminary Technical Data
LSB + 2
MSB – 2
LSB + 1
LSB
LSB
2
S mode. LRCLK is low for the left
LSB + 2
LSB + 1
LSB
MSB
MSB + 1
MSB