adsp-21462 Analog Devices, Inc., adsp-21462 Datasheet - Page 32

• Manufacturer Part Number: adsp-21462
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
Memory Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 28. Memory Write
1
2
3
4
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
AMI_ACK delay/setup: System must meet t
The falling edge of AMI_MSx is referenced.
Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
See
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
Test Conditions on Page 52
AMI_ADDR
AMI_DATA
AMI_ACK
AMI_WR
AMI_RD
MSx
—
Bus Master
AMI_ACK Delay from Address, Selects
AMI_ACK Delay from AMI_WR Low
Address, Selects to AMI_WR Deasserted
Address, Selects to AMI_WR Low
AMI_WR Pulse Width
Data Setup Before AMI_WR High
Address Hold After AMI_WR Deasserted
Data Hold After AMI_WR Deasserted
Data Disable After AMI_WR Deasserted
AMI_WR High to AMI_WR, AMI_RD Low
Data Disable Before AMI_RD Low
AMI_WR Low to Data Enabled
—
for calculation of hold times given capacitive and dc loads.
Bus Master
DAAK
t
t
DAWL
DAAK
t
WDE
, or t
DSAK
, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t
t
DSAK
Figure 19. Memory Write
Rev. PrC | Page 32 of 62 | January 2009
2
1, 3
1, 2
4
2
S
t
DDR2_CLK
DAWH
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
H = (number of hold cycles specified in AMICTLx register) x t
WW
t
—
DDWH
Bus Master
Preliminary Technical Data
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
DATRWH
t
DWHD
t
t
t
DWHA
WWR
DDWR
DAAK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DDR2_CLK
or t
DSAK
.