adsp-21462 Analog Devices, Inc., adsp-21462 Datasheet - Page 45

• Manufacturer Part Number: adsp-21462
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the TBD × FS clock.
Table 42. S/PDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
SCLK frequency is TBD x FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
(DATA CHANNEL A/B)
DAI_P20-1
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20-1
DAI_P20-1
(SCLK)
(FS)
Rev. PrC | Page 45 of 62 | January 2009
DRIVE EDGE
t
t
HOFSI
HDTI
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
t
DFSI
t
SCLKIW
t
DDTI
Min
TBD
TBD
TBD
TBD
TBD
SAMPLE EDGE
Max
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns