dsp56f802ta80 Freescale Semiconductor, Inc, dsp56f802ta80 Datasheet - Page 24

• Manufacturer Part Number: dsp56f802ta80
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.5.2
24
Frequency for the PLL
PLL output frequency
PLL stabilization time
PLL stabilization time
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
User Manual. ZCLK = f
3.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
Figure 3-8 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25
Will not exceed 60MHz for the DSP56F802TA60 device.
Phase Locked Loop Timing
11
10
Characteristic
8
5
9
7
6
2
4
4
op
1
0
0
-40
o
to +85
o
10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
to 0
o
o
C
C
56F802 Technical Data, Rev. 9
Table 3-9 PLL Timing
Symbol
f
out
f
t
t
osc
plls
plls
/2
out
Min
40
—
—
4
/2, please refer to the OCCS chapter in the
Typ
100
10
—
8
Freescale Semiconductor
Max
200
80
10
—
3
o
MHz
MHz
Unit
C
ms
ms