dsp56f802ta80 Freescale Semiconductor, Inc, dsp56f802ta80 Datasheet - Page 29

• Manufacturer Part Number: dsp56f802ta80
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.10 JTAG Timing
Freescale Semiconductor
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at
sampling time. (1pf)
TCK frequency of operation
TCK cycle time
TCK clock pulse width
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
Operating Conditions:
ADC analog input
Characteristic
Figure 3-13 Equivalent Analog Input Circuit
2
1
V
SS
Table 3-14 JTAG Timing
= V
56F802 Technical Data, Rev. 9
SSA
= 0 V, V
2
DD
= V
DDA
Symbol
t
TRST
= 3.0–3.6 V, T
t
f
t
t
t
t
t
PW
OP
DH
CY
DS
DV
TS
3
1, 3
A
Min
100
DC
0.4
1.2
50
50
—
—
= –40° to +85°C, C
4
Max
26.6
23.5
10
—
—
—
—
—
L
≤
50 pF
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
JTAG Timing
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