dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 32

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dsp56167

Manufacturer Part Number
dsp56167
Description
Advance Information 16-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Specifications
Clock Operation
2-6
Note:
Num
1
2
3
4
5
6
7
8
EXTAL
1.
2.
3.
4.
Frequency of Operation (EXTAL input)
Instruction Cycle Time = 2 T
Wait State = T
EXTAL cycle period
EXTAL rise time
EXTAL fall time
EXTAL width high
EXTAL width low
Rise and fall time may be relaxed to 12 ns maximum if the EXTAL input frequency is 20 MHz. If
E
MHz and 60 MHz, rise and fall time should meet the specified value (3 ns maximum).
The duty cycle may be relaxed to 43–57% if the EXTAL input frequency is 20 MHz. If the EXTAL
input frequency is between 20MHz and 40MHz, the duty cycle should be such that T
12 ns minimum. If the EXTAL input frequency is between 40 MHz and 60 MHz, the duty cycle
should be such that T
T = I
cycle of the external clock input.
Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC
coupled and at V
f
is between 20 MHz and 40 MHz, rise and fall time should be 4 ns maximum. If E
CYC
/4 is used in the electrical characteristics. The exact length of each T is affected by the duty
C
T
7
Characteristics
H
= 2 T
1
1
DD
2,3,4
2,3,4
/2 when DC coupled.
H
Figure 2-3 External Clock Timing
(48–52% duty cycle)
4
(48–52% duty cycle)
and T
Table 2-5 Clock Operation
DSP56167/D, Rev. 1
L
meet the specified values in the 60 MHz column (8 ns minimum).
T
C
8
L
2
6
Symbol
I
WS
CYC
T
T
T
E
H
C
L
f
Min
16.6
16.6
33
0
8
8
60 MHz
Max
60
3
3
10%
90%
f
MOTOROLA
is between 40
H
V
Midpoint
V
5
and T
IHC
ILC
MHz
Unit
AA0774
ns
ns
ns
ns
ns
ns
ns
L
are

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