saa7199b NXP Semiconductors, saa7199b Datasheet - Page 8

• Manufacturer Part Number: saa7199b
• Description: Digital Video Encoder Denc Genlock-capable
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The SAA7199B is a digital video encoder that translates
digital RGB, YUV or 8-bit indexed colour signals into the
analog PAL/NTSC output signals Y (luminance), C
(4.43/3.58 MHz chrominance) and CVBS (composite
signal including sync).
Four different modes are selectable (Table 18):
The input data rate (pixel sequence) has an integer
relationship to the number of horizontal clock cycles
(Table 1). A sufficient stable external clock signal ensures
correct encoding. The generated clock frequency in the
GENLOCK mode may deviate by 7% depending on the
reference signal which is corresponding to its input sync
signal. The clock will be nominal in the GENLOCK mode
when the reference signal is absent (nominal with crystal
oscillator accuracy for TV time constants, and nominal
The on-chip colour conversion matrix provides “ CCIR 601”
code-compatible transcoding of RGB to YUV data.
RGB data out of bounds, with respect to “CCIR 601”
specification, can be clipped to prevent over-loading of the
colour modulator. RGB data input can be either in linear
colour space or in gamma-corrected colour space.
YUV data must be gamma-corrected in accordance with
“ CCIR 601” . This circuit operates primarily in a 24-bit
colour space (3
different data formats (4 : 1 : 1, 4 : 2 : 2 and 4 : 4 : 4) plus
8-bit indexed pseudo-colour space operations (FMT-bits in
Table 8).
RGB CLUTs on-chip provide gamma-correction and/or
other CLUT functions. They consist of programmable
tables to be loaded independently, and they generate
24-bit gamma-corrected output signals from 24-bit data of
one of the input formats or from 8-bit indexed
pseudo-colour data.
1996 Sep 27
1.4% for VCR time constants).
Stand-alone mode (horizontal and vertical timings are
generated)
Slave mode (stand-alone unit that accepts external
horizontal and vertical timing), and optional real time
information for subcarrier/clock from a digital colour
decoder
GENLOCK mode (GENLOCK capabilities are achieved
in conjunction with determined ICs)
Test mode (only clock signal is required).
Digital Video Encoder (DENC)
GENLOCK-capable
8-bit) but can also accommodate
8
Required modulation is performed. The digital YUV data is
encoded in accordance with standards “RS-170A ”
(composite NTSC) and “CCIR 624-4 ” (composite
PAL-B/G). S-video output signal is available (Y/C) also
some sub-standard output signals (STD-bits in Table 12).
A 7.5 IRE set-up level is automatically selected in the
60 Hz mode, but not selected in the 50 Hz mode.
The analog signal outputs can drive directly into
terminated 75
recommended (Figs 3, 13 and 14). Analog post-filtering is
required (LP in Fig.3).
GENLOCK to an external reference signal is achieved by
addition of a video ADC and a clock generator
combination. Thus, the system is enabled to lock on a
stable video source or to a stable VCR source (normal
playback). The SAA7199B, the ADC and the clock
generator combination (Fig.3) form a control loop
achieving a highly stable line-locked clock. The clock has
to be generated by a crystal oscillator without this
availability. The GENLOCK mode is not available in a
single device set-up.
Control interface
The SAA7199B supports a standard parallel MPU
interface and the serial I
direct access to internal control registers and colour
tables. Update is possible at any time, excluding
coincident internal reading and external writing of the
same cell (the current pixel value could be destroyed).
The two interfaces of Table 2 are selected automatically.
However, the I
interface is selected by CS = LOW. No simultaneous
access may occur. I
each other and have access to common registers
controlled via a common internal bus. The programmer
can use virtually identical programs.
The internal memory space is devided into the look-up
table and the control table, each with its own 8-bit address
register used as a pointer for specific location.
This address register is provided with auto-incrementation
and can be written by only one addressing.
The look-up table contains three banks of 256 bytes.
Therefore, each read or write cycle must access all three
banks in a pre-determined order. The support logic is part
of the control interface.
2
C-bus control is inactive when the MPU
coaxial lines, a passive external filter is
2
C-bus and MPU control complement
2
C-bus interface. The MPU has
Product specification
SAA7199B