saa7199b NXP Semiconductors, saa7199b Datasheet - Page 9

• Manufacturer Part Number: saa7199b
• Description: Digital Video Encoder Denc Genlock-capable
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Timing (see Fig.3)
The reference to generate internal clocks from LLC in
GENLOCK operation with SAA7197 is CREF
CREF =
In this event input CLKSEL is HIGH and the SRC-bit = 1.
In non-GENLOCK operation the signal from CLKIN is used
and LDV is clock reference (input CLKSEL = 0;
SCR-bit = CPR-bit = 0).
Pins LLC and CLKIN are tied together when no switching
between LLC and CLKIN is applied. In Fig.3 it is assumed
that LLC and CLKIN are double the pixel clock frequency
of CREF and LDV respectively.
CREF must be at the same frequency (or constant HIGH
or LOW) when LLC is at pixel clock frequency. CPR-bit = 1
if CLKIN is at pixel clock frequency.
The buffered CLKO signal is always delayed. LLC or
CLKIN signals are in accordance with CLKSEL.
Mapping
The method of mapping external control signals on to the
internal bus is simple. The MPU-bus contains the signals
as shown in Table 4 (names in chip-internal
nomenclature).
Table 1 Pixel relationships
Table 2 Access to the control interface
1996 Sep 27
640 (square)
720
768
720
SDA
SCL
A1, A0
R/W
CS
GPSW
RESET
ACTIVE PIXELS
Digital Video Encoder (DENC)
GENLOCK-capable
PER LINE
SYMBOL
LLC
-----------
2
.
I
I
MPU-bus address inputs
read/write control input
chip select input; I
general purpose switch output (bit of control register)
reset input signal; active-LOW
2
2
FIELD RATE
C-bus serial data line (bidirectional)
C-bus clock line
(Hz)
60
60
50
50
2
C-bus disabled when LOW
MULTIPLES OF LINE
FREQUENCY
780
858
944
864
9
Bit allocation
The Bit Allocation Map (BAM) shows the individual control
signals, used to control the different operational modes of
the circuit. The I
The SAA7199B also has an MPU-bus interface for direct
microcontroller connection. The BAM shown in Table 6
resembles the I
parallel bus; the control registers are indexed from
00H to 0FH. Auto-incrementation is applied.
Digital-to-analog converters
The converters use a combination of resistor chains with
low-impedance output buffers. The bottom output voltage
is 200 mV to reduce integral non-linearity errors.
The analog signal, without load on output pin, is between
0.2 and 2.2 V. Figure 16 shows the application for
1.23 V/75
Each digital-to-analog converter has its own supply pin for
the purpose of decoupling. V
the resistor chains of the three DACs. The accuracy of this
supply voltage directly influences the output amplitudes.
The current CUR into pin 71 is 0.3 mA (V
R
but increases the integral non-linearity.
DESCRIPTION
64-71
= 20 k ); a larger current improves the bandwidth
PIXCLK OUTPUT SIGNAL
outputs, using the serial 25 + 22
2
2
C-bus type but can be also used for the
C-bus is normally used for control.
(MHz)
12.27
14.75
13.5
13.5
DDA4
is the supply voltage for
Product specification
SAA7199B
DDA4
CRYSTAL
24.576
24.576
(MHz)
= 5 V;
26.8
26.8
resistors.