at40k-fft ATMEL Corporation, at40k-fft Datasheet - Page 2

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at40k-fft

Manufacturer Part Number
at40k-fft
Description
Fast Fourier Transform Intellectual Property Core At40k Fpgas
Manufacturer
ATMEL Corporation
Datasheet
Operation and Interfacing
Figure 1. Internal architecture of the FFT processor.
Figure 1 shows the architecture of the FFT processor. The
design is based on the radix-2 decimation in frequency
algorithm and employs in-place computation to optimize
memory usage.
Figure 2. Example FFT processor configuration 1.
Figure 3. Example FFT processor configuration 2.
2
Data input
AT40K-FFT
port
Clock
input
Imag
input
Input
Real
Processor
Address
Address
Counter
Counter
clock
8
12
12
1 2
1 2
FIFO
FIFO
Processor
8
FFT
Processor
Factor ROM
12
12
Data RAM
clock
Butterfly
Twiddle
12
Processor
To operate the processor data must first be loaded into the
internal RAM. The processor is then instructed to compute
the FFT, overwriting the input data in the RAM with the
results. On completion of the FFT the results can be read
out from the RAM via the output data port.
Address
FFT
Data
24
8
Address
Counter
Control
1 2
Proc
1 2
Address
8
Data
24
8
Proc
Control port
Data output
port

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