at40k-fft ATMEL Corporation, at40k-fft Datasheet - Page 5

• Manufacturer Part Number: at40k-fft
• Description: Fast Fourier Transform Intellectual Property Core At40k Fpgas
• Manufacturer: ATMEL Corporation

Address Generators
The design employs two address generators to control the
input and output of data from the data RAM. One is used to
generate the read addresses and the other the write
addresses. Both produce the same address pattern,
though they are skewed in phase by 9 cycles, i.e. the
length of the butterfly pipeline.
The data address generators are based on an 8 bit accu-
mulator where the carry out signal is connected to the carry
in signal. The accumulator increment is provide by a
Johnson counter which increments every 256 cycles. The
data address generators feature tristate outputs to discon-
nect them from the address busses while data is trans-
ferred into or out of the chip.
The twiddle factor address generator produces a different
address sequence. Here an 8 bit binary counter is
employed, the output bits of which are ANDed with a mask-
ing function. This masking function is provided by an 8-bit
shift register which steps through the following pattern
00000001b, 00000011b, 00000111b, etc., once every 256
cycles.
Controller
The controller synchronizes the operation of all the other
components. It contains a state machine closely coupled to
a counter to generate all the control signals required.
The state machine provides a simple two line control port
(START and BUSY) to enable external devices to initiate
processing and monitor its completion.
Design Capture and Layout
The design was entered via schematic capture using Work-
view Office. This design method was employed to provide
good design visibility to users.
Extensive use was made of user macros to ensure high
performance layouts for sub components.
The device targeted for the design was the AT40K30. Utili-
zation of the part was as follows:
Design Simulation
The design was simulated using the gate level simulator
ViewSim. Both functional and post layout simulations were
performed to confirm the correct operation of the design.
A MatLab script was employed to generated the input data
files for the simulation. This same script was also used to
read the results files from the simulation and check them
against the MatLab FFT function.
Timing Analysis
Timing analysis of the design indicated a maximum clock
speed of 21.2 MHz when using the AT40K30 part. Investi-
gations into the limiting data path revealed this to be the
delay from the twiddle factor address counter output,
through the asynchronous twiddle factor ROM to the butter-
fly’s twiddle factor input. Clearly, conversion of the twiddle
ROM from asynchronous to synchronous operation would
be a starting point for improving the design’s performance.
Logic Cells: 1114/1600 = 69.6%
RAM Cells: 48/100 = 48%
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