ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 183
ep1sgx25d
Manufacturer Part Number
ep1sgx25d
Description
Stratix Gx Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1SGX25D.pdf
(272 pages)
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Altera Corporation
February 2005
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL (clock
inputs)
Differential HSTL (clock
outputs)
Differential SSTL (clock
outputs)
3.3-V GTL
3.3-V GTL+
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
SSTL-18 class I
SSTL-18 class II
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
Table 4–28. I/O Support by Bank (Part 1 of 2)
I/O Standard
Table 4–28
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
shows I/O standard support for each I/O bank.
Left Banks
(1 & 2)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix GX Device Handbook, Volume 1
Enhanced PLL External
Stratix GX Architecture
Clock Output Banks
(9, 10, 11 & 12)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
4–117
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