ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 61

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 3–9. Fast PLL Clocks & Data Input
Altera Corporation
August 2005
Data input
Clock A'
Clock B'
Clock C'
Clock D'
Clock C
Clock D
Clock A
Clock B
D0
D1
Protocols, Training Pattern & DPA Lock Time
The dynamic phase aligner uses a fast PLL for clock multiplication, and
the dynamic phase selector for the phase detection and alignment. The
dynamic phase aligner uses the high-speed clock out of the dynamic
phase selector to deserialize high-speed data and the receiver's source
synchronous operations.
At each rising edge of the clock, the dynamic phase selector determines
the phase difference between the clock and the data and automatically
compensates for the phase difference between the data and clock.
D2
D3
D4
Source-Synchronous Signaling With DPA
Stratix GX Device Handbook, Volume 1
D5
D n
3–11